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llvm-mirror/test/CodeGen/Hexagon/cmpb_pred.ll
Krzysztof Parzyszek 14957cb237 [Hexagon] Always generate mux out of predicated transfers if possible
HexagonGenMux would collapse pairs of predicated transfers if it assumed
that the predicated .new forms cannot be created. Turns out that generating
mux is preferable in almost all cases.
Introduce an option -hexagon-gen-mux-threshold that controls the minimum
distance between the instruction defining the predicate and the later of
the two transfers. If the distance is closer than the threshold, mux will
not be generated. Set the threshold to 0 by default.

llvm-svn: 328346
2018-03-23 18:43:09 +00:00

90 lines
1.8 KiB
LLVM

; RUN: llc -march=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s
; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
target triple = "hexagon"
@Enum_global = external global i8
define i32 @Func_3(i32) nounwind readnone {
entry:
; CHECK-NOT: mux
%conv = and i32 %0, 255
%cmp = icmp eq i32 %conv, 2
%selv = zext i1 %cmp to i32
ret i32 %selv
}
define i32 @Func_3b(i32) nounwind readonly {
entry:
; CHECK-NOT: mux
%1 = load i8, i8* @Enum_global, align 1
%2 = trunc i32 %0 to i8
%cmp = icmp ne i8 %1, %2
%selv = zext i1 %cmp to i32
ret i32 %selv
}
define i32 @Func_3c(i32) nounwind readnone {
entry:
; CHECK-NOT: mux
%conv = and i32 %0, 255
%cmp = icmp eq i32 %conv, 2
%selv = zext i1 %cmp to i32
ret i32 %selv
}
define i32 @Func_3d(i32) nounwind readonly {
entry:
; CHECK-NOT: mux
%1 = load i8, i8* @Enum_global, align 1
%2 = trunc i32 %0 to i8
%cmp = icmp eq i8 %1, %2
%selv = zext i1 %cmp to i32
ret i32 %selv
}
define i32 @Func_3e(i32) nounwind readonly {
entry:
; CHECK-NOT: mux
%1 = load i8, i8* @Enum_global, align 1
%2 = trunc i32 %0 to i8
%cmp = icmp eq i8 %1, %2
%selv = zext i1 %cmp to i32
ret i32 %selv
}
define i32 @Func_3f(i32) nounwind readnone {
entry:
; CHECK-NOT: mux
%conv = and i32 %0, 255
%cmp = icmp ugt i32 %conv, 2
%selv = zext i1 %cmp to i32
ret i32 %selv
}
define i32 @Func_3g(i32) nounwind readnone {
entry:
; CHECK-NOT: mux
%conv = and i32 %0, 255
%cmp = icmp ult i32 %conv, 3
%selv = zext i1 %cmp to i32
ret i32 %selv
}
define i32 @Func_3h(i32) nounwind readnone {
entry:
; CHECK-NOT: mux
%conv = and i32 %0, 254
%cmp = icmp ult i32 %conv, 2
%selv = zext i1 %cmp to i32
ret i32 %selv
}
define i32 @Func_3i(i32) nounwind readnone {
entry:
; CHECK-NOT: mux
%conv = and i32 %0, 254
%cmp = icmp ugt i32 %conv, 1
%selv = zext i1 %cmp to i32
ret i32 %selv
}