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fe9991c322
1. Add pseudos PS_vloadrv_ai and PS_vstorerv_ai: those are now used for single vector registers in loadRegFromStackSlot (and store...). 2. Remove pseudos PS_vloadrwu_ai and PS_vstorerwu_ai. The alignment is now checked when expanding spill pseudos (both in frame lowering and in expand-post-ra-pseudos), and a proper instruction is generated. 3. Update MachineMemOperands when dealigning vector spill slots. 4. Return vector predicate registers in getCallerSavedRegs.
17 lines
433 B
YAML
17 lines
433 B
YAML
# RUN: llc -march=hexagon -run-pass prologepilog %s -o - | FileCheck %s
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# Check that the spill of $q0 uses unaligned store instruction.
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# CHECK: V6_vS32Ub_ai $r30, -128, killed $v0
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---
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name: test
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tracksRegLiveness: true
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stack:
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- { id: 0, type: variable-sized, offset: 0, alignment: 1 }
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- { id: 1, type: spill-slot, size: 128, alignment: 128 }
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body: |
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bb.0:
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liveins: $q0
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PS_vstorerq_ai %stack.1, 0, $q0
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...
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