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llvm-mirror/test/MC
Zequan Wu 59b9ad16d6 [CodeGen] emit CG profile for COFF object file
I forgot to add emission of CG profile for COFF object file, when adding the support (https://reviews.llvm.org/D81775)

Differential Revision: https://reviews.llvm.org/D87811
2020-09-18 10:57:54 -07:00
..
AArch64 [MC] [Win64EH] Write packed ARM64 epilogues if possible 2020-09-11 10:31:04 +03:00
AMDGPU [AMDGPU] gfx1030 test update. NFC. 2020-09-16 13:56:16 -07:00
ARM [MC] Resolve the difference of symbols in consecutive MCDataFragements 2020-09-09 12:35:43 -07:00
AsmParser [MC] Support infix operator ! 2020-07-30 23:25:53 -07:00
AVR [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex 2020-07-12 08:14:52 -07:00
BPF
COFF [CodeGen] emit CG profile for COFF object file 2020-09-18 10:57:54 -07:00
Disassembler [PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests 2020-09-17 18:20:54 -05:00
ELF [MC] Allow .org directives in SHT_NOBITS sections 2020-09-11 15:12:42 -07:00
Hexagon [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
Lanai
MachO [MC] Resolve the difference of symbols in consecutive MCDataFragements 2020-09-09 12:35:43 -07:00
Mips Revert "Reland D64327 [MC][ELF] Allow STT_SECTION referencing SHF_MERGE on REL targets" 2020-08-07 10:56:33 -07:00
MSP430 [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
PowerPC [PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests 2020-09-17 18:20:54 -05:00
RISCV [RISCV] add the MC layer support of riscv vector Zvamo extension 2020-08-27 14:11:38 +08:00
Sparc [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SystemZ [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
VE [VE] Support symbol with offset in assembly 2020-07-07 04:16:51 +09:00
WebAssembly [WebAssembly] Add assembly syntax for mutable globals 2020-09-11 11:11:02 -07:00
X86 [X86] Always use 16-bit displacement in 16-bit mode when there is no base or index register. 2020-09-15 19:31:48 -07:00