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AlignedBundling
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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AMX
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[X86-64] Support Intel AMX instructions
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2020-07-02 08:57:04 +08:00 |
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Inputs
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[NFC][X86] Simplify test cases for branch align
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2020-03-16 16:30:29 +08:00 |
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3DNow.s
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2011-09-06-NoNewline.s
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abs8.s
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address-size.s
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AES-32.s
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AES-64.s
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align-branch-32bit.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-align.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-basic.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-boundary-default.s
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[NFC][X86] Simplify test cases for branch align
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2020-03-16 16:30:29 +08:00 |
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align-branch-bundle.s
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[X86] Enable multibyte NOPs in 64-bit mode for padding/alignment.
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2020-07-01 23:59:01 -07:00 |
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align-branch-enhanced-relaxation.s
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[X86][MC] Support enhanced relaxation for branch align
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2020-04-08 19:08:19 +08:00 |
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align-branch-fused.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-general.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-hardcode.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-mixed.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-necessary.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-negative.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-pad-max-prefix.s
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[X86] Enable multibyte NOPs in 64-bit mode for padding/alignment.
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2020-07-01 23:59:01 -07:00 |
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align-branch-prefix.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-relax-all.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-section-size.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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align-branch-section-type.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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align-branch-single.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-system.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-branch-variant-symbol.s
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[NFC][test] Refine tests for branch align
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2020-04-11 13:04:52 +08:00 |
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align-via-padding-corner.s
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[X86][MC] Disable Prefix padding after hardcode/prefix
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2020-04-01 09:49:52 +08:00 |
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align-via-padding.s
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[X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form
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2020-03-26 08:28:59 -07:00 |
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align-via-relaxation.s
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[X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form
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2020-03-26 08:28:59 -07:00 |
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avx512_bf16_vl-encoding.s
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avx512_bf16-encoding.s
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avx512-encodings.s
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avx512-err.s
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[X86][llvm-mc] Make the suffix matcher more accurate.
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2020-05-27 14:45:17 +08:00 |
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avx512bitalg-encoding.s
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avx512bw-encoding.s
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avx512gfni-encoding.s
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avx512ifma-encoding.s
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avx512ifmavl-encoding.s
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avx512vaes-encoding.s
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avx512vbmi2-encoding.s
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avx512vbmi2vl-encoding.s
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avx512vbmi-encoding.s
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avx512vl_bitalg-encoding.s
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avx512vl_gfni-encoding.s
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avx512vl_vaes-encoding.s
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avx512vl_vnni-encoding.s
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avx512vl-encoding.s
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avx512vlvpclmul.s
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avx512vnni-encoding.s
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avx512vp2intersectvl-att.s
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avx512vp2intersectvl-intel.s
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avx512vpclmul.s
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avx5124fmaps-encoding.s
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avx5124vnniw-encoding.s
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AVX2-32.s
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AVX2-64.s
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AVX512F_512-32.s
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AVX512F_512-64.s
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AVX512F_SCALAR-32.s
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AVX512F_SCALAR-64.s
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avx_vaes-encoding.s
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AVX-32.s
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AVX-64.s
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AVXAES-32.s
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AVXAES-64.s
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BMI1-32.s
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BMI1-64.s
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BMI2-32.s
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BMI2-64.s
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CET-32.s
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CET-64.s
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cet-encoding.s
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cfi_def_cfa-crash.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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cfi-open-within-another-crash.s
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cfi-scope-errors.s
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cfi-scope-unclosed.s
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check-end-of-data-region.s
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CLFLUSHOPT-32.s
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CLFLUSHOPT-64.s
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CLFSH-32.s
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CLFSH-64.s
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CLWB-32.s
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CLWB-64.s
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CLZERO-32.s
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CLZERO-64.s
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code16-32-64.s
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[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
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2020-03-05 18:05:28 -08:00 |
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code16gcc.s
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[X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode.
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2020-07-27 21:11:42 -07:00 |
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compact-unwind.s
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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crlf.test
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data-prefix16.s
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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data-prefix32.s
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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data-prefix64.s
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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data-prefix-fail.s
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directive-arch.s
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[X86] Parse and ignore .arch directives
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2020-07-30 08:30:06 -07:00 |
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disassemble-zeroes.s
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[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
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2020-03-05 18:05:28 -08:00 |
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dwarf-size-field-overflow.test
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encoder-fail.s
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error-reloc.s
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eval-fill.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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expand-var.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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F16C-32.s
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F16C-64.s
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faultmap-section-parsing.s
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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fde-reloc.s
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fixup-cpu-mode.s
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FMA-32.s
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FMA-64.s
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fp-setup-macho.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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FXSAVE64-64.s
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FXSAVE-32.s
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FXSAVE-64.s
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gather.s
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gfni-encoding.s
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gnux32-dwarf-gen.s
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hex-immediates.s
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i386-darwin-frame-register.ll
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Fix typo in comment
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2020-04-09 10:36:00 +01:00 |
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I86-32.s
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I86-64.s
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I186-32.s
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I186-64.s
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I286-32.s
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[X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register.
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2020-07-15 23:51:37 -07:00 |
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I286-64.s
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[X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register.
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2020-07-15 23:51:37 -07:00 |
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I386-32.s
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I386-64.s
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I486-32.s
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I486-64.s
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imm-comments.s
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index-operations.s
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inline-asm-obj.ll
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intel-syntax-2.s
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intel-syntax-32.s
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intel-syntax-ambiguous.s
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intel-syntax-avx512_bf16_vl.s
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intel-syntax-avx512_bf16.s
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intel-syntax-avx512-error.s
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intel-syntax-avx512.s
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intel-syntax-bitwise-ops.s
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intel-syntax-directional-label.s
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intel-syntax-encoding.s
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intel-syntax-error.s
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intel-syntax-hex.s
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intel-syntax-invalid-basereg.s
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intel-syntax-invalid-scale.s
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intel-syntax-print.ll
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intel-syntax-ptr-sized.s
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intel-syntax-unsized-memory.s
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intel-syntax-var-offset.ll
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intel-syntax-x86-64-avx512_bf16_vl.s
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intel-syntax-x86-64-avx512_bf16.s
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intel-syntax-x86-64-avx512f_vl.s
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intel-syntax-x86-64-avx.s
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intel-syntax-x86-avx512dq_vl.s
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intel-syntax-x86-avx512vbmi_vl.s
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intel-syntax.s
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invalid_opcode.s
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invalid-sleb.s
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INVPCID-32.s
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INVPCID-64.s
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large-bss.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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line-table-sections.s
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lit.local.cfg
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LWP-32.s
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LWP-64.s
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lwp-x86_64.s
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lwp.s
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macho-reloc-errors-x86_64.s
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macho-reloc-errors-x86.s
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macho-uleb.s
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MMX-32.s
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MMX-64.s
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mpx-encodings.s
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no-elf-compact-unwind.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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padlock.s
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[X86] Force VIA PadLock crypto instructions to emit a 0xF3 prefix when they encode to match what GNU as does.
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2020-06-11 12:59:21 -07:00 |
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PKU-32.s
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PKU-64.s
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POPCNT-32.s
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POPCNT-64.s
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PPRO-32.s
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PPRO-64.s
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pr22004.s
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pr22028.s
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pr27884.s
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pr28547.s
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pr32530.s
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pr37425.s
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pr38826.s
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PREFETCH-32.s
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PREFETCH-64.s
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prefix-padding-32.s
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[Tests] Add test coverage for prefix selection logic
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2020-03-16 17:27:44 -07:00 |
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prefix-padding-64.s
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[Tests] Add test coverage for prefix selection logic
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2020-03-16 17:27:44 -07:00 |
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RDPMC-32.s
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RDPMC-64.s
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RDRAND-32.s
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RDRAND-64.s
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RDSEED-32.s
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RDSEED-64.s
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RDTSCP-32.s
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RDTSCP-64.s
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RDWRFSGS-64.s
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relax-insn.s
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relax-offset.s
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[MC] Recalculate fragment offsets after relaxation
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2020-03-17 14:48:05 -07:00 |
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reloc-directive-elf-32.s
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[MC][X86] Make .reloc support arbitrary relocation types
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2020-03-27 13:33:15 -07:00 |
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reloc-directive-elf-64.s
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[MC][X86] Make .reloc support arbitrary relocation types
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2020-03-27 13:33:15 -07:00 |
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reloc-directive.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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reloc-macho.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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reloc-undef-global.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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ret.s
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return-column.s
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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RTM.s
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SHA-32.s
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SHA-64.s
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shuffle-comments.s
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signed-coff-pcrel.s
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space-err.s
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SSE2-32.s
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SSE2-64.s
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SSE3-32.s
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SSE3-64.s
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SSE4a-32.s
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SSE4a-64.s
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SSE41-32.s
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SSE41-64.s
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SSE42-32.s
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SSE42-64.s
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SSE_PREFETCH-32.s
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SSE_PREFETCH-64.s
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SSE-32.s
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SSE-64.s
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SSEMXCSR-32.s
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SSEMXCSR-64.s
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SSSE3-32.s
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SSSE3-64.s
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stackmap-nops.ll
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stdcall.s
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SVM-32.s
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SVM-64.s
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tlsdesc-32.s
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
|
2020-03-15 17:46:23 -07:00 |
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tlsdesc-64.s
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[llvm-objdump] Print target address with evaluateMemoryOperandAddress()
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2020-04-27 09:43:51 -07:00 |
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unused_reg_var_assign.s
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validate-inst-att.s
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validate-inst-intel.s
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variant-diagnostics.s
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VMFUNC-32.s
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VMFUNC-64.s
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vpclmulqdq.s
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VTX-32.s
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VTX-64.s
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x86_64-asm-match.s
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x86_64-avx-clmul-encoding.s
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x86_64-avx-encoding.s
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x86_64-bmi-encoding.s
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x86_64-directive-nops.s
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[X86] support .nops directive
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2020-08-03 11:50:56 -07:00 |
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x86_64-encoding.s
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x86_64-fma3-encoding.s
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x86_64-fma4-encoding.s
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x86_64-hle-encoding.s
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x86_64-imm-widths.s
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x86_64-rand-encoding.s
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x86_64-rtm-encoding.s
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x86_64-signed-reloc.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
|
2020-07-20 10:39:04 +01:00 |
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x86_64-sse4a.s
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x86_64-tbm-encoding.s
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x86_64-xop-encoding.s
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x86_directives.s
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x86_errors.s
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[X86] Add assembler support for {vex} prefix to match GNU as.
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2020-05-08 11:50:58 -07:00 |
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x86_long_nop.s
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
|
2020-03-15 17:46:23 -07:00 |
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x86_nop.s
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x86_operands.s
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x86-16.s
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[X86] Always use 16-bit displacement in 16-bit mode when there is no base or index register.
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2020-09-15 19:31:48 -07:00 |
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x86-32-avx512_vp2intersect-intel.s
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x86-32-avx512vp2intersect-att.s
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x86-32-avx.s
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x86-32-coverage.s
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[X86] Add TSXLDTRK instructions.
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2020-04-09 13:17:29 +08:00 |
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x86-32-fma3.s
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x86-32-ms-inline-asm.s
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x86-32.s
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[X86] Add assembler support for .d32 and .d8 mnemonic suffixes to control displacement size.
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2020-08-26 10:45:50 -07:00 |
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x86-64-avx512_bf16_vl-encoding.s
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x86-64-avx512_bf16-encoding.s
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x86-64-avx512_vp2intersect-intel.s
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x86-64-avx512bw_vl.s
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x86-64-avx512bw.s
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x86-64-avx512cd_vl.s
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x86-64-avx512cd.s
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x86-64-avx512dq_vl.s
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x86-64-avx512dq.s
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x86-64-avx512f_vl.s
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x86-64-avx512pf.s
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x86-64-avx512vp2intersect-att.s
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x86-64-avx512vp2intersectvl-att.s
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x86-64-avx512vp2intersectvl-intel.s
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x86-64-avx512vpopcntdq.s
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x86-64.s
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[X86] Add assembler support for .d32 and .d8 mnemonic suffixes to control displacement size.
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2020-08-26 10:45:50 -07:00 |
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x86-branch-relaxation.s
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[X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form
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2020-03-26 08:28:59 -07:00 |
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x86-directive-nops-errors.s
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[X86] support .nops directive
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2020-08-03 11:50:56 -07:00 |
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x86-directive-nops.s
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[X86] support .nops directive
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2020-08-03 11:50:56 -07:00 |
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x86-evenDirective.s
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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x86-GCC-inline-asm-Y-constraints.ll
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[X86] Remove support for Y0 constraint as an alias for Yz in inline assembly.
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2020-05-06 14:58:53 -07:00 |
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x86-itanium.ll
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x86-jcxz-loop-fixup.s
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x86-target-directives.s
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x86-windows-itanium-libcalls.ll
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X86_64-pku.s
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X87-32.s
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X87-64.s
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XOP-32.s
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XOP-64.s
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XSAVE-32.s
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XSAVE-64.s
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XSAVEC-32.s
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XSAVEC-64.s
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XSAVEOPT-32.s
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XSAVEOPT-64.s
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XSAVES-32.s
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XSAVES-64.s
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