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12cdca9076
Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
20 lines
852 B
ArmAsm
20 lines
852 B
ArmAsm
// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s > %t 2> %t.err
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// RUN: FileCheck < %t %s
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// RUN: FileCheck --check-prefix=CHECK-STDERR < %t.err %s
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// CHECK: vgatherdps %xmm2, (%rdi,%xmm2,2), %xmm2
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// CHECK-STDERR: warning: mask, index, and destination registers should be distinct
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vgatherdps %xmm2, (%rdi,%xmm2,2), %xmm2
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// CHECK: vpgatherdd (%r14,%zmm11,8), %zmm11 {%k1}
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// CHECK-STDERR: warning: index and destination registers should be distinct
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vpgatherdd (%r14, %zmm11,8), %zmm11 {%k1}
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// CHECK: vpgatherqd (%r14,%zmm11,8), %ymm11 {%k1}
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// CHECK-STDERR: warning: index and destination registers should be distinct
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vpgatherqd (%r14, %zmm11,8), %ymm11 {%k1}
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// CHECK: vpgatherdq (%r14,%ymm11,8), %zmm11 {%k1}
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// CHECK-STDERR: warning: index and destination registers should be distinct
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vpgatherdq (%r14, %ymm11,8), %zmm11 {%k1}
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