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29b969dda5
These features (fairly) recently got split out into their own feature, so we should make CodeGen use them when available. The main change here is that the check used to be based on the triple, but now it's based on CPU features. llvm-svn: 349355
67 lines
1.5 KiB
LLVM
67 lines
1.5 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
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; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
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; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
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; CHECK-LABEL: f0:
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; CHECK-NOT: ldrexd
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define i64 @f0(i64* %p) nounwind readonly {
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entry:
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%0 = load atomic i64, i64* %p seq_cst, align 8
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ret i64 %0
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}
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; CHECK-LABEL: f1:
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; CHECK-NOT: strexd
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define void @f1(i64* %p) nounwind readonly {
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entry:
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store atomic i64 0, i64* %p seq_cst, align 8
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ret void
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}
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; CHECK-LABEL: f2:
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; CHECK-NOT: ldrexd
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; CHECK-NOT: strexd
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define i64 @f2(i64* %p) nounwind readonly {
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entry:
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%0 = atomicrmw add i64* %p, i64 1 seq_cst
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ret i64 %0
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}
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; CHECK-LABEL: f3:
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; CHECK-V7: ldr
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; CHECK-V8: lda
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define i32 @f3(i32* %p) nounwind readonly {
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entry:
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%0 = load atomic i32, i32* %p seq_cst, align 4
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ret i32 %0
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}
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; CHECK-LABEL: f4:
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; CHECK-V7: ldrb
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; CHECK-V8: ldab
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define i8 @f4(i8* %p) nounwind readonly {
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entry:
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%0 = load atomic i8, i8* %p seq_cst, align 4
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ret i8 %0
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}
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; CHECK-LABEL: f5:
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; CHECK-V7: str
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; CHECK-V8: stl
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define void @f5(i32* %p) nounwind readonly {
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entry:
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store atomic i32 0, i32* %p seq_cst, align 4
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ret void
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}
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; CHECK-LABEL: f6:
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; CHECK-V7: ldrex
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; CHECK-V7: strex
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; CHECK-V8: ldaex
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; CHECK-V8: stlex
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define i32 @f6(i32* %p) nounwind readonly {
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entry:
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%0 = atomicrmw add i32* %p, i32 1 seq_cst
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ret i32 %0
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}
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