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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
112 lines
3.2 KiB
C++
112 lines
3.2 KiB
C++
//===-- GCNSchedStrategy.h - GCN Scheduler Strategy -*- C++ -*-------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
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#define LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
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#include "GCNRegPressure.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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namespace llvm {
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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class GCNSubtarget;
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/// This is a minimal scheduler strategy. The main difference between this
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/// and the GenericScheduler is that GCNSchedStrategy uses different
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/// heuristics to determine excess/critical pressure sets. Its goal is to
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/// maximize kernel occupancy (i.e. maximum number of waves per simd).
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class GCNMaxOccupancySchedStrategy : public GenericScheduler {
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friend class GCNScheduleDAGMILive;
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SUnit *pickNodeBidirectional(bool &IsTopNode);
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void pickNodeFromQueue(SchedBoundary &Zone, const CandPolicy &ZonePolicy,
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const RegPressureTracker &RPTracker,
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SchedCandidate &Cand);
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void initCandidate(SchedCandidate &Cand, SUnit *SU,
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bool AtTop, const RegPressureTracker &RPTracker,
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const SIRegisterInfo *SRI,
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unsigned SGPRPressure, unsigned VGPRPressure);
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unsigned SGPRExcessLimit;
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unsigned VGPRExcessLimit;
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unsigned SGPRCriticalLimit;
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unsigned VGPRCriticalLimit;
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unsigned TargetOccupancy;
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MachineFunction *MF;
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public:
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GCNMaxOccupancySchedStrategy(const MachineSchedContext *C);
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SUnit *pickNode(bool &IsTopNode) override;
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void initialize(ScheduleDAGMI *DAG) override;
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void setTargetOccupancy(unsigned Occ) { TargetOccupancy = Occ; }
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};
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class GCNScheduleDAGMILive : public ScheduleDAGMILive {
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const GCNSubtarget &ST;
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SIMachineFunctionInfo &MFI;
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// Occupancy target at the beginning of function scheduling cycle.
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unsigned StartingOccupancy;
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// Minimal real occupancy recorder for the function.
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unsigned MinOccupancy;
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// Scheduling stage number.
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unsigned Stage;
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// Current region index.
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size_t RegionIdx;
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// Vecor of regions recorder for later rescheduling
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SmallVector<std::pair<MachineBasicBlock::iterator,
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MachineBasicBlock::iterator>, 32> Regions;
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// Region live-in cache.
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SmallVector<GCNRPTracker::LiveRegSet, 32> LiveIns;
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// Region pressure cache.
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SmallVector<GCNRegPressure, 32> Pressure;
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// Temporary basic block live-in cache.
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DenseMap<const MachineBasicBlock*, GCNRPTracker::LiveRegSet> MBBLiveIns;
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// Return current region pressure.
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GCNRegPressure getRealRegPressure() const;
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// Compute and cache live-ins and pressure for all regions in block.
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void computeBlockPressure(const MachineBasicBlock *MBB);
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public:
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GCNScheduleDAGMILive(MachineSchedContext *C,
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std::unique_ptr<MachineSchedStrategy> S);
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void schedule() override;
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void finalizeSchedule() override;
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};
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} // End namespace llvm
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#endif // GCNSCHEDSTRATEGY_H
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