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1311b33688
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138 llvm-svn: 357801
111 lines
4.9 KiB
TableGen
111 lines
4.9 KiB
TableGen
//===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 conditional move and set on condition
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// instructions.
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//
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//===----------------------------------------------------------------------===//
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// CMOV instructions.
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let isCodeGenOnly = 1, ForceDisassemble = 1 in {
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let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
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isCommutable = 1, SchedRW = [WriteCMOV] in {
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def CMOV16rr
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: I<0x40, MRMSrcRegCC, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, ccode:$cond),
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"cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst,
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(X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>,
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TB, OpSize16;
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def CMOV32rr
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: I<0x40, MRMSrcRegCC, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, ccode:$cond),
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"cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst,
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(X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>,
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TB, OpSize32;
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def CMOV64rr
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:RI<0x40, MRMSrcRegCC, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, ccode:$cond),
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"cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst,
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(X86cmov GR64:$src1, GR64:$src2, imm:$cond, EFLAGS))]>, TB;
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}
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let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
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SchedRW = [WriteCMOV.Folded, WriteCMOV.ReadAfterFold] in {
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def CMOV16rm
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: I<0x40, MRMSrcMemCC, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2, ccode:$cond),
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"cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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imm:$cond, EFLAGS))]>, TB, OpSize16;
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def CMOV32rm
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: I<0x40, MRMSrcMemCC, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2, ccode:$cond),
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"cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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imm:$cond, EFLAGS))]>, TB, OpSize32;
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def CMOV64rm
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:RI<0x40, MRMSrcMemCC, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2, ccode:$cond),
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"cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
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imm:$cond, EFLAGS))]>, TB;
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} // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
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} // isCodeGenOnly = 1, ForceDisassemble = 1
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// SetCC instructions.
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let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
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def SETCCr : I<0x90, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
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"set${cond}\t$dst",
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[(set GR8:$dst, (X86setcc imm:$cond, EFLAGS))]>,
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TB, Sched<[WriteSETCC]>;
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def SETCCm : I<0x90, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
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"set${cond}\t$dst",
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[(store (X86setcc imm:$cond, EFLAGS), addr:$dst)]>,
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TB, Sched<[WriteSETCCStore]>;
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} // Uses = [EFLAGS]
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multiclass CMOV_SETCC_Aliases<string Cond, int CC> {
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def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
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(CMOV16rr GR16:$dst, GR16:$src, CC), 0>;
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def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
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(CMOV16rm GR16:$dst, i16mem:$src, CC), 0>;
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def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
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(CMOV32rr GR32:$dst, GR32:$src, CC), 0>;
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def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
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(CMOV32rm GR32:$dst, i32mem:$src, CC), 0>;
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def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
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(CMOV64rr GR64:$dst, GR64:$src, CC), 0>;
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def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
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(CMOV64rm GR64:$dst, i64mem:$src, CC), 0>;
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def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
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def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
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}
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defm : CMOV_SETCC_Aliases<"o" , 0>;
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defm : CMOV_SETCC_Aliases<"no", 1>;
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defm : CMOV_SETCC_Aliases<"b" , 2>;
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defm : CMOV_SETCC_Aliases<"ae", 3>;
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defm : CMOV_SETCC_Aliases<"e" , 4>;
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defm : CMOV_SETCC_Aliases<"ne", 5>;
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defm : CMOV_SETCC_Aliases<"be", 6>;
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defm : CMOV_SETCC_Aliases<"a" , 7>;
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defm : CMOV_SETCC_Aliases<"s" , 8>;
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defm : CMOV_SETCC_Aliases<"ns", 9>;
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defm : CMOV_SETCC_Aliases<"p" , 10>;
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defm : CMOV_SETCC_Aliases<"np", 11>;
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defm : CMOV_SETCC_Aliases<"l" , 12>;
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defm : CMOV_SETCC_Aliases<"ge", 13>;
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defm : CMOV_SETCC_Aliases<"le", 14>;
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defm : CMOV_SETCC_Aliases<"g" , 15>;
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// SALC is an undocumented instruction. Information for this instruction can be found
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// here http://www.rcollins.org/secrets/opcodes/SALC.html
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// Set AL if carry.
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let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in {
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def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>;
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}
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