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797611111a
Add DestructiveBinaryImm SQSHLU patterns and tests. These patterns allow the SQSHLU instruction to match with a MOVPRFX. Differential Revision: https://reviews.llvm.org/D76728
59 lines
2.8 KiB
LLVM
59 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -asm-verbose=0 < %s | FileCheck %s
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;
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; SQSHLU
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;
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define <vscale x 16 x i8> @sqshlu_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
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; CHECK-LABEL: sqshlu_i8:
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; CHECK: movprfx z0.b, p0/z, z0.b
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; CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #2
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; CHECK-NEXT: ret
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%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %a_z,
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i32 2)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @sqshlu_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
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; CHECK-LABEL: sqshlu_i16:
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; CHECK: movprfx z0.h, p0/z, z0.h
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; CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #3
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; CHECK-NEXT: ret
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%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %a_z,
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i32 3)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @sqshlu_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
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; CHECK-LABEL: sqshlu_i32:
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; CHECK: movprfx z0.s, p0/z, z0.s
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; CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #29
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; CHECK-NEXT: ret
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%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %a_z,
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i32 29)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @sqshlu_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
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; CHECK-LABEL: sqshlu_i64:
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; CHECK: movprfx z0.d, p0/z, z0.d
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; CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #62
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; CHECK-NEXT: ret
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%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %a_z,
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i32 62)
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ret <vscale x 2 x i64> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)
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