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6f935bda6e
This commit allows v_cndmask_b32_e64 with abs, neg source modifiers on src0, src1 to be assembled and disassembled. This does appear to be allowed, even though they are floating point modifiers and the operand type is b32. To do this, I added src0_modifiers and src1_modifiers to the MachineInstr, which involved fixing up several places in codegen and mir tests. Differential Revision: https://reviews.llvm.org/D59191 Change-Id: I69bf4a8c73ebc65744f6110bb8fc4e937d79fbea llvm-svn: 356398
35 lines
1.1 KiB
YAML
35 lines
1.1 KiB
YAML
# RUN: llc -march=amdgcn -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
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# CHECK: %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# CHECK: %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# CHECK: %4:vgpr_32 = COPY %3
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# CHECK: %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# CHECK: %6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# CHECK: %7:vgpr_32 = COPY %3
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---
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name: fold_cndmask
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: vgpr_32 }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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body: |
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bb.0.entry:
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%0 = IMPLICIT_DEF
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%1 = V_CNDMASK_B32_e64 0, 0, 0, 0, %0, implicit $exec
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%2 = V_CNDMASK_B32_e64 0, %1, 0, %1, %0, implicit $exec
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%3 = IMPLICIT_DEF
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%4 = V_CNDMASK_B32_e64 0, %3, 0, %3, %0, implicit $exec
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%5 = COPY %1
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%6 = V_CNDMASK_B32_e64 0, %5, 0, 0, %0, implicit $exec
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$vcc = IMPLICIT_DEF
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%7 = V_CNDMASK_B32_e32 %3, %3, implicit $exec, implicit $vcc
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...
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