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b83b98ad03
Add a new llvm.amdgcn.ballot intrinsic modeled on the ballot function in GLSL and other shader languages. It returns a bitfield containing the result of its boolean argument in all active lanes, and zero in all inactive lanes. This is intended to replace the existing llvm.amdgcn.icmp and llvm.amdgcn.fcmp intrinsics after a suitable transition period. Use the new intrinsic in the atomic optimizer pass. Differential Revision: https://reviews.llvm.org/D65088
94 lines
2.8 KiB
LLVM
94 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 < %s | FileCheck %s
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declare i32 @llvm.amdgcn.ballot.i32(i1)
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; Test ballot(0)
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define i32 @test0() {
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; CHECK-LABEL: test0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 0)
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ret i32 %ballot
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}
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; Test ballot(1)
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define i32 @test1() {
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; CHECK-LABEL: test1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, exec_lo
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 1)
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ret i32 %ballot
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}
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; Test ballot of a non-comparison operation
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: v_cmp_ne_u32_e64 s4, 0, v0
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%trunc = trunc i32 %x to i1
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %trunc)
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ret i32 %ballot
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}
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; Test ballot of comparisons
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define i32 @test3(i32 %x, i32 %y) {
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; CHECK-LABEL: test3:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_cmp_eq_u32_e64 s4, v0, v1
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%cmp = icmp eq i32 %x, %y
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
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ret i32 %ballot
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}
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define i32 @test4(i32 %x) {
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; CHECK-LABEL: test4:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_cmp_lt_i32_e64 s4, 0x62, v0
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%cmp = icmp sge i32 %x, 99
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
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ret i32 %ballot
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}
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define i32 @test5(float %x, float %y) {
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; CHECK-LABEL: test5:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_cmp_gt_f32_e64 s4, v0, v1
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%cmp = fcmp ogt float %x, %y
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
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ret i32 %ballot
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}
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