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90d04d1194
Summary:
PHIs result register class is set to VGPR or SGPR depending on the cross block value divergence.
In some cases uniform PHI need to be converted to return VGPR to prevent the oddnumber of moves values from VGPR to SGPR and back.
PHI should certainly return VGPR if it has at least one VGPR input. This change adds the exception.
We don't want to convert uniform PHI to VGPRs in case the only VGPR input is a VGPR to SGPR COPY and definition od the
source VGPR in this COPY is move immediate.
bb.0:
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:sreg_32 = .....
bb.1:
%3:sreg_32 = PHI %1, %bb.3, %2, %bb.1
S_BRANCH %bb.3
bb.3:
%1:sreg_32 = COPY %0
S_BRANCH %bb.2
Reviewers: rampitec
Reviewed By: rampitec
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80434
98 lines
2.3 KiB
YAML
98 lines
2.3 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
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---
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# GCN_LABEL: phi_moveimm_input
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# GCN-NOT: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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# GCN: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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name: phi_moveimm_input
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%4:sreg_32 = COPY $sgpr0
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%5:sreg_32 = COPY $sgpr1
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bb.1:
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successors: %bb.2
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%2:sreg_32 = S_ADD_U32 %4, %5, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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%3:sreg_32 = PHI %1, %bb.3, %2, %bb.1
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.2
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%1:sreg_32 = COPY %0
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S_BRANCH %bb.2
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...
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---
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# GCN_LABEL: phi_moveimm_subreg_input
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# GCN-NOT: %{{[0-9]+}}:sreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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# GCN: %{{[0-9]+}}:vreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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name: phi_moveimm_subreg_input
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%4:sreg_32 = COPY $sgpr0
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%5:sreg_32 = COPY $sgpr1
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bb.1:
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successors: %bb.2
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undef %2.sub0:sreg_64 = S_ADD_U32 %4, %5, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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%3:sreg_64 = PHI %1, %bb.3, %2, %bb.1
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.2
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undef %1.sub0:sreg_64 = COPY %0
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S_BRANCH %bb.2
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...
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---
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# GCN_LABEL: phi_moveimm_bad_opcode_input
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# GCN-NOT: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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# GCN: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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name: phi_moveimm_bad_opcode_input
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1, $vgpr0
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%6:vgpr_32 = COPY $vgpr0
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%0:vgpr_32 = V_MOV_B32_sdwa 0, %6:vgpr_32, 0, 5, 2, 4, implicit $exec, implicit %6:vgpr_32(tied-def 0)
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%4:sreg_32 = COPY $sgpr0
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%5:sreg_32 = COPY $sgpr1
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bb.1:
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successors: %bb.2
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%2:sreg_32 = S_ADD_U32 %4, %5, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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%3:sreg_32 = PHI %1, %bb.3, %2, %bb.1
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.2
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%1:sreg_32 = COPY %0
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S_BRANCH %bb.2
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...
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