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b9148f5d85
Summary: Extend cachepolicy operand in the new VMEM buffer intrinsics to supply information whether the buffer data is swizzled. Also, propagate this information to MIR. Intrinsics updated: int_amdgcn_raw_buffer_load int_amdgcn_raw_buffer_load_format int_amdgcn_raw_buffer_store int_amdgcn_raw_buffer_store_format int_amdgcn_raw_tbuffer_load int_amdgcn_raw_tbuffer_store int_amdgcn_struct_buffer_load int_amdgcn_struct_buffer_load_format int_amdgcn_struct_buffer_store int_amdgcn_struct_buffer_store_format int_amdgcn_struct_tbuffer_load int_amdgcn_struct_tbuffer_store Furthermore, disable merging of VMEM buffer instructions in SI Load/Store optimizer, if the "swizzled" bit on the instruction is on. The default value of the bit is 0, meaning that data in buffer is linear and buffer instructions can be merged. There is no difference in the generated code with this commit. However, in the future it will be expected that front-ends use buffer intrinsics with correct "swizzled" bit set. Reviewers: arsenm, nhaehnle, tpr Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68200 llvm-svn: 373491
231 lines
6.3 KiB
YAML
231 lines
6.3 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: vmem_vcc_fallthrough
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# GCN: bb.1:
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_fallthrough
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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bb.1:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_branch_to_next
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# GCN: bb.1:
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_branch_to_next
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_fallthrough_no_hazard_too_far
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# GCN: bb.1:
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_fallthrough_no_hazard_too_far
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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$sgpr0 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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bb.1:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_fallthrough_no_hazard_nops
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# GCN: bb.1:
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_fallthrough_no_hazard_nops
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_NOP 4
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bb.1:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_branch_around
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# GCN: bb.2:
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_branch_around
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body: |
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bb.0:
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successors: %bb.2
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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S_NOP 0
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S_NOP 0
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S_NOP 0
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S_NOP 0
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bb.2:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_branch_backedge
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# GCN: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_branch_backedge
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body: |
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bb.0:
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successors: %bb.1
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$vgpr0 = IMPLICIT_DEF
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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bb.1:
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.0
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...
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# GCN-LABEL: name: vmem_vcc_min_of_two
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# GCN: bb.2:
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_min_of_two
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body: |
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bb.0:
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successors: %bb.2
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_NOP 0
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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bb.2:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_self_loop
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# GCN: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_self_loop
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body: |
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bb.0:
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successors: %bb.0
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$vgpr0 = IMPLICIT_DEF
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.0
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...
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# GCN-LABEL: name: vmem_vcc_min_of_two_self_loop1
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# GCN: bb.1:
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# GCN: $sgpr0 = S_MOV_B32 0
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_min_of_two_self_loop1
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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bb.1:
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successors: %bb.1
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$sgpr0 = S_MOV_B32 0
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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$vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.1
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...
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# GCN-LABEL: name: vmem_vcc_min_of_two_self_loop2
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# GCN: bb.1:
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# GCN: $sgpr0 = S_MOV_B32 0
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_min_of_two_self_loop2
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_NOP 0
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bb.1:
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successors: %bb.1
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$sgpr0 = S_MOV_B32 0
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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$vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.1
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...
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