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llvm-mirror/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
Tim Renouf f385f41c29 [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic
Allow the clamp modifier on vop3 int arithmetic instructions in assembly
and disassembly.

This involved adding a clamp operand to the affected instructions in MIR
and MC, and thus having to fix up several places in codegen and MIR
tests.

Differential Revision: https://reviews.llvm.org/D59267

Change-Id: Ic7775105f02a985b668fa658a0cd7837846a534e
llvm-svn: 356399
2019-03-18 19:35:44 +00:00

41 lines
1.3 KiB
YAML

# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
...
# GCN-LABEL: name: fold_imm_non_ssa{{$}}
# GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
# GCN: %2:vgpr_32 = V_ADD_I32_e32 456, %0, implicit-def $vcc, implicit $exec
name: fold_imm_non_ssa
tracksRegLiveness: true
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64 }
body: |
bb.0:
%0 = COPY undef %0
%0 = V_MOV_B32_e32 123, implicit $exec
%1 = V_MOV_B32_e32 456, implicit $exec
%2, $vcc = V_ADD_I32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: fold_partially_defined_superreg{{$}}
# GCN: %1:vgpr_32 = V_MOV_B32_e32 456, implicit $exec
# GCN: %2:vgpr_32 = V_ADD_I32_e32 123, %1, implicit-def $vcc, implicit $exec
name: fold_partially_defined_superreg
tracksRegLiveness: true
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vreg_64 }
body: |
bb.0:
undef %3.sub0 = V_MOV_B32_e32 123, implicit $exec, implicit-def %3
%1 = V_MOV_B32_e32 456, implicit $exec
%2, $vcc = V_ADD_I32_e64 %3.sub0, %1, 0, implicit $exec
S_ENDPGM 0
...