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b9148f5d85
Summary: Extend cachepolicy operand in the new VMEM buffer intrinsics to supply information whether the buffer data is swizzled. Also, propagate this information to MIR. Intrinsics updated: int_amdgcn_raw_buffer_load int_amdgcn_raw_buffer_load_format int_amdgcn_raw_buffer_store int_amdgcn_raw_buffer_store_format int_amdgcn_raw_tbuffer_load int_amdgcn_raw_tbuffer_store int_amdgcn_struct_buffer_load int_amdgcn_struct_buffer_load_format int_amdgcn_struct_buffer_store int_amdgcn_struct_buffer_store_format int_amdgcn_struct_tbuffer_load int_amdgcn_struct_tbuffer_store Furthermore, disable merging of VMEM buffer instructions in SI Load/Store optimizer, if the "swizzled" bit on the instruction is on. The default value of the bit is 0, meaning that data in buffer is linear and buffer instructions can be merged. There is no difference in the generated code with this commit. However, in the future it will be expected that front-ends use buffer intrinsics with correct "swizzled" bit set. Reviewers: arsenm, nhaehnle, tpr Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68200 llvm-svn: 373491
104 lines
2.8 KiB
YAML
104 lines
2.8 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx803 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
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--- |
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define amdgpu_ps void @irreducible_loop() {
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ret void
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}
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define amdgpu_ps void @irreducible_loop_extended() {
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ret void
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}
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...
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---
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# GCN-LABEL: name: irreducible_loop{{$}}
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# GCN: S_LOAD_DWORDX4_IMM
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# GFX8: S_WAITCNT 127{{$}}
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# GFX9: S_WAITCNT 49279{{$}}
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# GCN: S_BUFFER_LOAD_DWORD_IMM
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# GFX8: S_WAITCNT 127{{$}}
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# GFX9: S_WAITCNT 49279{{$}}
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# GCN: S_CMP_GE_I32
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name: irreducible_loop
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body: |
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bb.0:
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successors: %bb.3, %bb.2
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S_CBRANCH_VCCZ %bb.2, implicit $vcc
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S_BRANCH %bb.3
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bb.1:
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successors: %bb.3, %bb.2
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S_CBRANCH_VCCNZ %bb.3, implicit $vcc
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bb.2:
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successors: %bb.3
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renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 0, 0, 0
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renamable $sgpr3 = S_BUFFER_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0
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bb.3:
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successors: %bb.1, %bb.4
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S_CMP_GE_I32 renamable $sgpr2, renamable $sgpr3, implicit-def $scc
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S_CBRANCH_SCC0 %bb.1, implicit killed $scc
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bb.4:
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S_ENDPGM 0
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...
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# GCN-LABEL: name: irreducible_loop_extended
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# GCN: S_LOAD_DWORDX4_IMM
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# GFX8: S_WAITCNT 127{{$}}
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# GFX9: S_WAITCNT 49279{{$}}
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# GCN: BUFFER_STORE_DWORD_OFFEN_exact
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# GFX8: S_WAITCNT 127{{$}}
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# GFX9: S_WAITCNT 49279{{$}}
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# GCN: BUFFER_STORE_DWORD_OFFEN_exact
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# GCN: S_LOAD_DWORDX4_IMM
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# GFX8: S_WAITCNT 127{{$}}
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# GFX9: S_WAITCNT 49279{{$}}
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# GCN: BUFFER_ATOMIC_ADD_OFFSET_RTN
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# GCN: S_WAITCNT 3952
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# GCN: FLAT_STORE_DWORD
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# GCN: S_ENDPGM 0
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name: irreducible_loop_extended
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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$sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr2_sgpr3, 0, 0, 0
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S_CBRANCH_VCCZ %bb.2, implicit $vcc
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bb.1:
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successors: %bb.2
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BUFFER_STORE_DWORD_OFFEN_exact killed renamable $vgpr3, renamable $vgpr2, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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bb.2:
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successors: %bb.3, %bb.6
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S_CBRANCH_VCCNZ %bb.6, implicit $vcc
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bb.3:
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successors: %bb.4, %bb.5
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BUFFER_STORE_DWORD_OFFEN_exact killed renamable $vgpr3, killed renamable $vgpr2, killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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S_CBRANCH_VCCNZ %bb.5, implicit $vcc
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bb.4:
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successors: %bb.5
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renamable $sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM killed renamable $sgpr2_sgpr3, 64, 0, 0
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renamable $vgpr2 = BUFFER_ATOMIC_ADD_OFFSET_RTN killed renamable $vgpr2, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, implicit $exec
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bb.5:
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successors: %bb.6
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bb.6:
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FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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S_ENDPGM 0
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...
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