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e2e0a9d886
The default promotion for the add_sat/sub_sat nodes currently does:
ANY_EXTEND iN to iM
SHL by M-N
[US][ADD|SUB]SAT
L/ASHR by M-N
If the promoted add_sat or sub_sat node is not legal, this can produce code
that effectively does a lot of shifting (and requiring large constants to be
materialised) just to use the overflow flag. It is simpler to just do the
saturation manually, using the higher bitwidth addition and a min/max against
the saturating bounds. That is what this patch attempts to do.
Differential Revision: https://reviews.llvm.org/D68926
llvm-svn: 375211
186 lines
5.4 KiB
LLVM
186 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
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; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
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; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
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declare i4 @llvm.uadd.sat.i4(i4, i4)
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declare i8 @llvm.uadd.sat.i8(i8, i8)
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declare i16 @llvm.uadd.sat.i16(i16, i16)
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declare i32 @llvm.uadd.sat.i32(i32, i32)
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declare i64 @llvm.uadd.sat.i64(i64, i64)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-T1-LABEL: func:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: blo .LBB0_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: movs r0, #0
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; CHECK-T1-NEXT: mvns r0, r0
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; CHECK-T1-NEXT: .LBB0_2:
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: func:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: adds r0, r0, r1
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; CHECK-T2-NEXT: it hs
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; CHECK-T2-NEXT: movhs.w r0, #-1
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: adds r0, r0, r1
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; CHECK-ARM-NEXT: mvnhs r0, #0
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y)
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ret i32 %tmp
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; CHECK-T1-LABEL: func2:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
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; CHECK-T1-NEXT: push {r4, r5, r7, lr}
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; CHECK-T1-NEXT: movs r5, #0
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; CHECK-T1-NEXT: adds r4, r0, r2
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; CHECK-T1-NEXT: adcs r1, r3
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; CHECK-T1-NEXT: mov r3, r5
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; CHECK-T1-NEXT: adcs r3, r5
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; CHECK-T1-NEXT: mvns r2, r5
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; CHECK-T1-NEXT: cmp r3, #0
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; CHECK-T1-NEXT: mov r0, r2
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; CHECK-T1-NEXT: beq .LBB1_3
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: cmp r3, #0
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; CHECK-T1-NEXT: beq .LBB1_4
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; CHECK-T1-NEXT: .LBB1_2:
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; CHECK-T1-NEXT: mov r1, r2
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; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
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; CHECK-T1-NEXT: .LBB1_3:
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; CHECK-T1-NEXT: mov r0, r4
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; CHECK-T1-NEXT: cmp r3, #0
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; CHECK-T1-NEXT: bne .LBB1_2
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; CHECK-T1-NEXT: .LBB1_4:
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; CHECK-T1-NEXT: mov r2, r1
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; CHECK-T1-NEXT: mov r1, r2
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; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
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;
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; CHECK-T2-LABEL: func2:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: adds r0, r0, r2
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; CHECK-T2-NEXT: mov.w r12, #0
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; CHECK-T2-NEXT: adcs r1, r3
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; CHECK-T2-NEXT: adcs r2, r12, #0
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; CHECK-T2-NEXT: itt ne
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; CHECK-T2-NEXT: movne.w r0, #-1
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; CHECK-T2-NEXT: movne.w r1, #-1
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func2:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: adds r0, r0, r2
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; CHECK-ARM-NEXT: mov r12, #0
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; CHECK-ARM-NEXT: adcs r1, r1, r3
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; CHECK-ARM-NEXT: adcs r2, r12, #0
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; CHECK-ARM-NEXT: mvnne r0, #0
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; CHECK-ARM-NEXT: mvnne r1, #0
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y)
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ret i64 %tmp
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}
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define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
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; CHECK-T1-LABEL: func16:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: ldr r1, .LCPI2_0
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; CHECK-T1-NEXT: cmp r0, r1
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; CHECK-T1-NEXT: blo .LBB2_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB2_2:
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; CHECK-T1-NEXT: bx lr
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; CHECK-T1-NEXT: .p2align 2
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; CHECK-T1-NEXT: @ %bb.3:
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; CHECK-T1-NEXT: .LCPI2_0:
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; CHECK-T1-NEXT: .long 65535 @ 0xffff
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;
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; CHECK-T2-LABEL: func16:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: add r1, r0
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; CHECK-T2-NEXT: movw r0, #65535
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; CHECK-T2-NEXT: cmp r1, r0
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; CHECK-T2-NEXT: it lo
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; CHECK-T2-NEXT: movlo r0, r1
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func16:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: add r1, r0, r1
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; CHECK-ARM-NEXT: movw r0, #65535
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; CHECK-ARM-NEXT: cmp r1, r0
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; CHECK-ARM-NEXT: movlo r0, r1
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y)
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ret i16 %tmp
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}
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define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
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; CHECK-T1-LABEL: func8:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: cmp r0, #255
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; CHECK-T1-NEXT: blo .LBB3_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: movs r0, #255
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; CHECK-T1-NEXT: .LBB3_2:
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: func8:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: add r0, r1
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; CHECK-T2-NEXT: cmp r0, #255
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; CHECK-T2-NEXT: it hs
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; CHECK-T2-NEXT: movhs r0, #255
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func8:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: add r0, r0, r1
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; CHECK-ARM-NEXT: cmp r0, #255
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; CHECK-ARM-NEXT: movhs r0, #255
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y)
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ret i8 %tmp
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}
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define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
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; CHECK-T1-LABEL: func3:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: cmp r0, #15
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; CHECK-T1-NEXT: blo .LBB4_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: movs r0, #15
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; CHECK-T1-NEXT: .LBB4_2:
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: func3:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: add r0, r1
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; CHECK-T2-NEXT: cmp r0, #15
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; CHECK-T2-NEXT: it hs
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; CHECK-T2-NEXT: movhs r0, #15
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func3:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: add r0, r0, r1
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; CHECK-ARM-NEXT: cmp r0, #15
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; CHECK-ARM-NEXT: movhs r0, #15
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y)
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ret i4 %tmp
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}
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