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https://github.com/RPCS3/llvm-mirror.git
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a3957bd3b3
This patch adds a simple Cortex-M4 schedule, renaming the existing M3 schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM: https://developer.arm.com/docs/ddi0439/latest Most of these are 1, with the important exception being loads taking 2 cycles. A few others are also higher, but I don't believe they make a large difference. I've repurposed the M3 schedule as the latencies are mostly the same between the two cores, with the M4 having more FP and DSP instructions. We also turn on MISched and UseAA for the cores that now use this. It also adds some schedule Write's to various instruction to make things simpler. Differential Revision: https://reviews.llvm.org/D54142 llvm-svn: 360768
159 lines
3.1 KiB
LLVM
159 lines
3.1 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7m -mcpu=cortex-m7 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BP
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; RUN: llc < %s -mtriple=thumbv7m -mcpu=cortex-m3 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOBP
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declare void @otherfn()
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; CHECK-LABEL: triangle1:
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; CHECK: itt ne
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; CHECK: movne
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; CHECK: strne
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define i32 @triangle1(i32 %n, i32* %p) {
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entry:
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%tobool = icmp eq i32 %n, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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store i32 1, i32* %p, align 4
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br label %if.end
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if.end:
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tail call void @otherfn()
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ret i32 0
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}
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; CHECK-LABEL: triangle2:
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; CHECK-BP: itttt ne
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; CHECK-BP: movne
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; CHECK-BP: strne
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; CHECK-BP: movne
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; CHECK-BP: strne
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; CHECK-NOBP: cbz
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; CHECK-NOBP: movs
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; CHECK-NOBP: str
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; CHECK-NOBP: movs
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; CHECK-NOBP: str
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define i32 @triangle2(i32 %n, i32* %p, i32* %q) {
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entry:
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%tobool = icmp eq i32 %n, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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store i32 1, i32* %p, align 4
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store i32 2, i32* %q, align 4
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br label %if.end
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if.end:
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tail call void @otherfn()
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ret i32 0
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}
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; CHECK-LABEL: triangle3:
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; CHECK: cbz
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; CHECK: movs
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; CHECK: str
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; CHECK: movs
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; CHECK: str
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; CHECK: movs
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; CHECK: str
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define i32 @triangle3(i32 %n, i32* %p, i32* %q, i32* %r) {
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entry:
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%tobool = icmp eq i32 %n, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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store i32 1, i32* %p, align 4
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store i32 2, i32* %q, align 4
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store i32 3, i32* %r, align 4
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br label %if.end
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if.end:
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tail call void @otherfn()
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ret i32 0
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}
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; CHECK-LABEL: diamond1:
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; CHECK: itee eq
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; CHECK: ldreq
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; CHECK: strne
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define i32 @diamond1(i32 %n, i32* %p) {
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entry:
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%tobool = icmp eq i32 %n, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then:
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store i32 %n, i32* %p, align 4
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br label %if.end
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if.else:
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%0 = load i32, i32* %p, align 4
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br label %if.end
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if.end:
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%n.addr.0 = phi i32 [ %n, %if.then ], [ %0, %if.else ]
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tail call void @otherfn()
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ret i32 %n.addr.0
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}
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; CHECK-LABEL: diamond2:
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; CHECK-BP: cbz
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; CHECK-BP: str
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; CHECK-BP: str
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; CHECK-BP: b
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; CHECK-BP: str
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; CHECK-BP: add
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; CHECK-NOBP: ittee
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; CHECK-NOBP: streq
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; CHECK-NOBP: addeq
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; CHECK-NOBP: strne
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; CHECK-NOBP: strne
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define i32 @diamond2(i32 %n, i32* %p, i32* %q) {
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entry:
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%tobool = icmp eq i32 %n, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then:
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store i32 %n, i32* %p, align 4
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%arrayidx = getelementptr inbounds i32, i32* %p, i32 2
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store i32 %n, i32* %arrayidx, align 4
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br label %if.end
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if.else:
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store i32 %n, i32* %q, align 4
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%0 = add i32 %n, 10
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br label %if.end
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if.end:
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%n.addr.0 = phi i32 [ %n, %if.then ], [ %0, %if.else ]
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tail call void @otherfn()
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ret i32 %n.addr.0
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}
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; CHECK-LABEL: diamond3:
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; CHECK: cbz
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; CHECK: movs
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; CHECK: str
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; CHECK: b
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; CHECK: ldr
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; CHECK: ldr
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; CHECK: adds
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define i32 @diamond3(i32 %n, i32* %p, i32* %q) {
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entry:
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%tobool = icmp eq i32 %n, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then:
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store i32 1, i32* %p, align 4
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br label %if.end
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if.else:
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%0 = load i32, i32* %p, align 4
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%1 = load i32, i32* %q, align 4
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%add = add nsw i32 %1, %0
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br label %if.end
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if.end:
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%n.addr.0 = phi i32 [ %n, %if.then ], [ %add, %if.else ]
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tail call void @otherfn()
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ret i32 %n.addr.0
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}
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