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995207ffa7
The test file has pairs of tests that are logically equivalent: https://rise4fun.com/Alive/2zQ %t4 = and i8 %t1, 8 %t5 = zext i8 %t4 to i16 %sh = shl i16 %t5, 2 %t6 = add i16 %sh, %t0 => %t4 = and i8 %t1, 8 %sh2 = shl i8 %t4, 2 %z5 = zext i8 %sh2 to i16 %t6 = add i16 %z5, %t0 ...so if we can fold the shift op into LEA in the 1st pattern, then we should be able to do the same in the 2nd pattern (unnecessary 'movzbl' is a separate bug I think). We don't want to do this any sooner though because that would conflict with generic transforms that try to narrow the width of the shift. Differential Revision: https://reviews.llvm.org/D60789 llvm-svn: 358622
184 lines
5.3 KiB
LLVM
184 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+slow-3ops-lea | FileCheck %s -check-prefixes=CHECK,SLOW
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; RUN: llc < %s -mtriple=x86_64-- -mattr=-slow-3ops-lea | FileCheck %s -check-prefixes=CHECK,FAST
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define i16 @and_i8_zext_shl_add_i16(i16 %t0, i8 %t1) {
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; CHECK-LABEL: and_i8_zext_shl_add_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: leal (%rdi,%rsi,4), %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%t4 = and i8 %t1, 8
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%t5 = zext i8 %t4 to i16
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%sh = shl i16 %t5, 2
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%t6 = add i16 %sh, %t0
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ret i16 %t6
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}
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define i16 @and_i8_shl_zext_add_i16(i16 %t0, i8 %t1) {
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; CHECK-LABEL: and_i8_shl_zext_add_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andb $8, %sil
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; CHECK-NEXT: movzbl %sil, %eax
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; CHECK-NEXT: leal (%rdi,%rax,4), %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%t4 = and i8 %t1, 8
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%sh = shl i8 %t4, 2
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%t5 = zext i8 %sh to i16
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%t6 = add i16 %t5, %t0
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ret i16 %t6
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}
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define i32 @and_i8_zext_shl_add_i32(i32 %t0, i8 %t1) {
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; CHECK-LABEL: and_i8_zext_shl_add_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: leal (%rdi,%rsi,8), %eax
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; CHECK-NEXT: retq
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%t4 = and i8 %t1, 8
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%t5 = zext i8 %t4 to i32
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%sh = shl i32 %t5, 3
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%t6 = add i32 %sh, %t0
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ret i32 %t6
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}
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define i32 @and_i8_shl_zext_add_i32(i32 %t0, i8 %t1) {
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; CHECK-LABEL: and_i8_shl_zext_add_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andb $8, %sil
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; CHECK-NEXT: movzbl %sil, %eax
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; CHECK-NEXT: leal (%rdi,%rax,8), %eax
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; CHECK-NEXT: retq
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%t4 = and i8 %t1, 8
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%sh = shl i8 %t4, 3
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%t5 = zext i8 %sh to i32
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%t6 = add i32 %t5, %t0
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ret i32 %t6
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}
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define i32 @and_i16_zext_shl_add_i32(i32 %t0, i16 %t1) {
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; CHECK-LABEL: and_i16_zext_shl_add_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: leal (%rdi,%rsi,4), %eax
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; CHECK-NEXT: retq
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%t4 = and i16 %t1, 8
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%t5 = zext i16 %t4 to i32
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%sh = shl i32 %t5, 2
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%t6 = add i32 %sh, %t0
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ret i32 %t6
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}
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define i32 @and_i16_shl_zext_add_i32(i32 %t0, i16 %t1) {
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; CHECK-LABEL: and_i16_shl_zext_add_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: leal (%rdi,%rsi,4), %eax
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; CHECK-NEXT: retq
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%t4 = and i16 %t1, 8
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%sh = shl i16 %t4, 2
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%t5 = zext i16 %sh to i32
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%t6 = add i32 %t5, %t0
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ret i32 %t6
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}
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define i64 @and_i8_zext_shl_add_i64(i64 %t0, i8 %t1) {
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; CHECK-LABEL: and_i8_zext_shl_add_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: leaq (%rdi,%rsi,2), %rax
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; CHECK-NEXT: retq
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%t4 = and i8 %t1, 8
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%t5 = zext i8 %t4 to i64
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%sh = shl i64 %t5, 1
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%t6 = add i64 %sh, %t0
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ret i64 %t6
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}
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define i64 @and_i8_shl_zext_add_i64(i64 %t0, i8 %t1) {
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; CHECK-LABEL: and_i8_shl_zext_add_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andb $8, %sil
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; CHECK-NEXT: movzbl %sil, %eax
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; CHECK-NEXT: leaq (%rdi,%rax,2), %rax
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; CHECK-NEXT: retq
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%t4 = and i8 %t1, 8
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%sh = shl i8 %t4, 1
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%t5 = zext i8 %sh to i64
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%t6 = add i64 %t5, %t0
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ret i64 %t6
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}
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define i64 @and_i32_zext_shl_add_i64(i64 %t0, i32 %t1) {
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; CHECK-LABEL: and_i32_zext_shl_add_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: leaq (%rdi,%rsi,8), %rax
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; CHECK-NEXT: retq
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%t4 = and i32 %t1, 8
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%t5 = zext i32 %t4 to i64
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%sh = shl i64 %t5, 3
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%t6 = add i64 %sh, %t0
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ret i64 %t6
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}
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define i64 @and_i32_shl_zext_add_i64(i64 %t0, i32 %t1) {
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; CHECK-LABEL: and_i32_shl_zext_add_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: leaq (%rdi,%rsi,8), %rax
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; CHECK-NEXT: retq
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%t4 = and i32 %t1, 8
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%sh = shl i32 %t4, 3
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%t5 = zext i32 %sh to i64
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%t6 = add i64 %t5, %t0
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ret i64 %t6
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}
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; Negative test - shift can't be converted to scale factor.
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define i64 @and_i32_zext_shl_add_i64_overshift(i64 %t0, i32 %t1) {
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; CHECK-LABEL: and_i32_zext_shl_add_i64_overshift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: shlq $4, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: retq
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%t4 = and i32 %t1, 8
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%t5 = zext i32 %t4 to i64
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%sh = shl i64 %t5, 4
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%t6 = add i64 %sh, %t0
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ret i64 %t6
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}
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define i64 @and_i32_shl_zext_add_i64_overshift(i64 %t0, i32 %t1) {
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; CHECK-LABEL: and_i32_shl_zext_add_i64_overshift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: shll $4, %esi
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: retq
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%t4 = and i32 %t1, 8
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%sh = shl i32 %t4, 4
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%t5 = zext i32 %sh to i64
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%t6 = add i64 %t5, %t0
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ret i64 %t6
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}
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