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013bed785d
This patch adds support for instructions performing bitwise operations on predicate vectors, including AND, BIC, EOR, NAND, NOR, ORN, ORR, and their status flag setting variants ANDS, BICS, EORS, NANDS, ORNS, ORRS. This patch also adds several aliases: orr p0.b, p1/z, p1.b, p1.b => mov p0.b, p1.b orrs p0.b, p1/z, p1.b, p1.b => movs p0.b, p1.b and p0.b, p1/z, p2.b, p2.b => mov p0.b, p1/z, p2.b ands p0.b, p1/z, p2.b, p2.b => movs p0.b, p1/z, p2.b eor p0.b, p1/z, p2.b, p1.b => not p0.b, p1/z, p2.b eors p0.b, p1/z, p2.b, p1.b => nots p0.b, p1/z, p2.b llvm-svn: 334906
28 lines
1.0 KiB
ArmAsm
28 lines
1.0 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Predicate register must have .b suffix
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nors p0.h, p0/z, p0.h, p1.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: nors p0.h, p0/z, p0.h, p1.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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nors p0.s, p0/z, p0.s, p1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: nors p0.s, p0/z, p0.s, p1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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nors p0.d, p0/z, p0.d, p1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: nors p0.d, p0/z, p0.d, p1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Operation only has zeroing predicate behaviour (p0/z).
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nors p0.b, p0/m, p1.b, p2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: nors p0.b, p0/m, p1.b, p2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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