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899b2f53e8
Summary:
This patch fixes a bug in the assembler that permitted a type suffix on
predicate registers when not expected. For instance, the following was
previously valid:
faddv h0, p0.q, z1.h
This bug was present in all SVE instructions containing predicates with
no type suffix and no predication form qualifier, i.e. /z or /m. The
latter instructions are already caught with an appropiate error message
by the assembler, e.g.:
.text
<stdin>:1:13: error: not expecting size suffix
cmpne p1.s, p0.b/z, z2.s, 0
^
A similar issue for SVE vector registers was fixed in:
https://reviews.llvm.org/D59636
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62942
llvm-svn: 362780
157 lines
6.0 KiB
ArmAsm
157 lines
6.0 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// invalid/missing predicate operation specifier
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prfb p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: prefetch hint expected
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// CHECK-NEXT: prfb p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #16, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: prefetch operand out of range, [0,15] expected
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// CHECK-NEXT: prfb #16, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb plil1keep, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: prefetch hint expected
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// CHECK-NEXT: prfb plil1keep, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #pldl1keep, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate value expected for prefetch operand
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// CHECK-NEXT: prfb #pldl1keep, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// invalid scalar + scalar addressing modes
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prfb #0, p0, [x0, #-33, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
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// CHECK-NEXT: prfb #0, p0, [x0, #-33, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, #32, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
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// CHECK-NEXT: prfb #0, p0, [x0, #32, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
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// CHECK-NEXT: prfb #0, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, x0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
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// CHECK-NEXT: prfb #0, p0, [x0, x0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, x0, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
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// CHECK-NEXT: prfb #0, p0, [x0, x0, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + vector addressing modes
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prfb #0, p0, [x0, z0.b]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: prfb #0, p0, [x0, z0.b]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.h]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: prfb #0, p0, [x0, z0.h]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.s, uxtw #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.s, uxtw #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.s, lsl #0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.s, lsl #0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.d, lsl #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.d, lsl #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.d, sxtw #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.d, sxtw #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector + immediate addressing modes
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prfb #0, p0, [z0.s, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
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// CHECK-NEXT: prfb #0, p0, [z0.s, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [z0.s, #32]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
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// CHECK-NEXT: prfb #0, p0, [z0.s, #32]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [z0.d, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
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// CHECK-NEXT: prfb #0, p0, [z0.d, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [z0.d, #32]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
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// CHECK-NEXT: prfb #0, p0, [z0.d, #32]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate
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prfb #0, p8, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: prfb #0, p8, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p7.b, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: prfb #0, p7.b, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p7.q, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: prfb #0, p7.q, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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prfb pldl1keep, p0, [x0, z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: prfb pldl1keep, p0, [x0, z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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prfb pldl1keep, p0, [x0, z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: prfb pldl1keep, p0, [x0, z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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