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899b2f53e8
Summary:
This patch fixes a bug in the assembler that permitted a type suffix on
predicate registers when not expected. For instance, the following was
previously valid:
faddv h0, p0.q, z1.h
This bug was present in all SVE instructions containing predicates with
no type suffix and no predication form qualifier, i.e. /z or /m. The
latter instructions are already caught with an appropiate error message
by the assembler, e.g.:
.text
<stdin>:1:13: error: not expecting size suffix
cmpne p1.s, p0.b/z, z2.s, 0
^
A similar issue for SVE vector registers was fixed in:
https://reviews.llvm.org/D59636
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62942
llvm-svn: 362780
123 lines
5.2 KiB
ArmAsm
123 lines
5.2 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-24, 21].
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st3d {z12.d, z13.d, z14.d}, p4, [x12, #-27, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
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// CHECK-NEXT: st3d {z12.d, z13.d, z14.d}, p4, [x12, #-27, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d {z7.d, z8.d, z9.d}, p3, [x1, #24, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
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// CHECK-NEXT: st3d {z7.d, z8.d, z9.d}, p3, [x1, #24, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Immediate not a multiple of three.
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st3d {z12.d, z13.d, z14.d}, p4, [x12, #-7, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
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// CHECK-NEXT: st3d {z12.d, z13.d, z14.d}, p4, [x12, #-7, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d {z7.d, z8.d, z9.d}, p3, [x1, #5, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
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// CHECK-NEXT: st3d {z7.d, z8.d, z9.d}, p3, [x1, #5, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st3d { z0.d, z1.d, z2.d }, p0, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d { z0.d, z1.d, z2.d }, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d { z0.d, z1.d, z2.d }, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate
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st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d {z2.d, z3.d, z4.d}, p7.b, [x15, #10, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st3d {z2.d, z3.d, z4.d}, p7.b, [x15, #10, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d {z2.d, z3.d, z4.d}, p7.q, [x15, #10, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st3d {z2.d, z3.d, z4.d}, p7.q, [x15, #10, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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st3d { }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: st3d { }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st3d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d { z0.d, z1.d, z2.b }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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// CHECK-NEXT: st3d { z0.d, z1.d, z2.b }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d { z0.d, z1.d, z3.d }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
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// CHECK-NEXT: st3d { z0.d, z1.d, z3.d }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st3d { v0.2d, v1.2d, v2.2d }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st3d { v0.2d, v1.2d, v2.2d }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z21.d, p5/z, z28.d
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st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z21, z28
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st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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