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899b2f53e8
Summary:
This patch fixes a bug in the assembler that permitted a type suffix on
predicate registers when not expected. For instance, the following was
previously valid:
faddv h0, p0.q, z1.h
This bug was present in all SVE instructions containing predicates with
no type suffix and no predication form qualifier, i.e. /z or /m. The
latter instructions are already caught with an appropiate error message
by the assembler, e.g.:
.text
<stdin>:1:13: error: not expecting size suffix
cmpne p1.s, p0.b/z, z2.s, 0
^
A similar issue for SVE vector registers was fixed in:
https://reviews.llvm.org/D59636
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62942
llvm-svn: 362780
61 lines
2.2 KiB
ArmAsm
61 lines
2.2 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid destination or source register.
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uminv d0, p7, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: uminv d0, p7, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uminv d0, p7, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: uminv d0, p7, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uminv d0, p7, z31.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: uminv d0, p7, z31.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uminv v0.2d, p7, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: uminv v0.2d, p7, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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uminv h0, p8, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: uminv h0, p8, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uminv h0, p7.b, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: uminv h0, p7.b, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uminv h0, p7.q, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: uminv h0, p7.q, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p7/z, z6.d
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uminv d0, p7, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: uminv d0, p7, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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uminv d0, p7, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: uminv d0, p7, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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