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ddd8ed6709
The Function can never be nullptr so we can return a reference. llvm-svn: 320884
233 lines
8.0 KiB
C++
233 lines
8.0 KiB
C++
//===- ARCRegisterInfo.cpp - ARC Register Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARC implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARCRegisterInfo.h"
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#include "ARC.h"
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#include "ARCInstrInfo.h"
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#include "ARCMachineFunctionInfo.h"
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#include "ARCSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "arc-reg-info"
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#define GET_REGINFO_TARGET_DESC
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#include "ARCGenRegisterInfo.inc"
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static void ReplaceFrameIndex(MachineBasicBlock::iterator II,
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const ARCInstrInfo &TII, unsigned Reg,
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unsigned FrameReg, int Offset, int StackSize,
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int ObjSize, RegScavenger *RS, int SPAdj) {
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assert(RS && "Need register scavenger.");
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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unsigned BaseReg = FrameReg;
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unsigned KillState = 0;
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if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) {
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// Loads can always be reached with LD_rlimm.
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BuildMI(MBB, II, dl, TII.get(ARC::LD_rlimm), Reg)
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.addReg(BaseReg)
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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MBB.erase(II);
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return;
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}
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if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) {
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// We need to use a scratch register to reach the far-away frame indexes.
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BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass);
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if (!BaseReg) {
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// We can be sure that the scavenged-register slot is within the range
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// of the load offset.
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const TargetRegisterInfo *TRI =
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MBB.getParent()->getSubtarget().getRegisterInfo();
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BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
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assert(BaseReg && "Register scavenging failed.");
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DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
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<< " for FrameReg=" << printReg(FrameReg, TRI)
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<< "+Offset=" << Offset << "\n");
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(void)TRI;
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RS->setRegUsed(BaseReg);
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}
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unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
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BuildMI(MBB, II, dl, TII.get(AddOpc))
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.addReg(BaseReg, RegState::Define)
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.addReg(FrameReg)
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.addImm(Offset);
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Offset = 0;
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KillState = RegState::Kill;
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}
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switch (MI.getOpcode()) {
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case ARC::LD_rs9:
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assert((Offset % 4 == 0) && "LD needs 4 byte alignment.");
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case ARC::LDH_rs9:
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case ARC::LDH_X_rs9:
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assert((Offset % 2 == 0) && "LDH needs 2 byte alignment.");
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case ARC::LDB_rs9:
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case ARC::LDB_X_rs9:
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DEBUG(dbgs() << "Building LDFI\n");
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BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg)
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.addReg(BaseReg, KillState)
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case ARC::ST_rs9:
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assert((Offset % 4 == 0) && "ST needs 4 byte alignment.");
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case ARC::STH_rs9:
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assert((Offset % 2 == 0) && "STH needs 2 byte alignment.");
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case ARC::STB_rs9:
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DEBUG(dbgs() << "Building STFI\n");
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BuildMI(MBB, II, dl, TII.get(MI.getOpcode()))
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.addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
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.addReg(BaseReg, KillState)
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case ARC::GETFI:
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DEBUG(dbgs() << "Building GETFI\n");
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BuildMI(MBB, II, dl,
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TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm))
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.addReg(Reg, RegState::Define)
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.addReg(FrameReg)
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.addImm(Offset);
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break;
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default:
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llvm_unreachable("Unhandled opcode.");
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}
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// Erase old instruction.
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MBB.erase(II);
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}
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ARCRegisterInfo::ARCRegisterInfo() : ARCGenRegisterInfo(ARC::BLINK) {}
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bool ARCRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
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return MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry();
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}
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const MCPhysReg *
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ARCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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return CSR_ARC_SaveList;
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}
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BitVector ARCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(ARC::ILINK);
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Reserved.set(ARC::SP);
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Reserved.set(ARC::GP);
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Reserved.set(ARC::R25);
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Reserved.set(ARC::BLINK);
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Reserved.set(ARC::FP);
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return Reserved;
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}
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bool ARCRegisterInfo::requiresRegisterScavenging(
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const MachineFunction &MF) const {
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return true;
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}
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bool ARCRegisterInfo::trackLivenessAfterRegAlloc(
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const MachineFunction &MF) const {
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return true;
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}
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bool ARCRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
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return true;
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}
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void ARCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
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int FrameIndex = FrameOp.getIndex();
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MachineFunction &MF = *MI.getParent()->getParent();
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const ARCInstrInfo &TII = *MF.getSubtarget<ARCSubtarget>().getInstrInfo();
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const ARCFrameLowering *TFI = getFrameLowering(MF);
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int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
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int ObjSize = MF.getFrameInfo().getObjectSize(FrameIndex);
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int StackSize = MF.getFrameInfo().getStackSize();
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int LocalFrameSize = MF.getFrameInfo().getLocalFrameSize();
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DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n");
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DEBUG(dbgs() << "<--------->\n");
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DEBUG(dbgs() << MI << "\n");
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DEBUG(dbgs() << "FrameIndex : " << FrameIndex << "\n");
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DEBUG(dbgs() << "ObjSize : " << ObjSize << "\n");
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DEBUG(dbgs() << "FrameOffset : " << Offset << "\n");
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DEBUG(dbgs() << "StackSize : " << StackSize << "\n");
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DEBUG(dbgs() << "LocalFrameSize : " << LocalFrameSize << "\n");
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(void)LocalFrameSize;
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// Special handling of DBG_VALUE instructions.
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if (MI.isDebugValue()) {
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unsigned FrameReg = getFrameRegister(MF);
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MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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return;
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}
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// fold constant into offset.
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Offset += MI.getOperand(FIOperandNum + 1).getImm();
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// TODO: assert based on the load type:
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// ldb needs no alignment,
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// ldh needs 2 byte alignment
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// ld needs 4 byte alignment
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DEBUG(dbgs() << "Offset : " << Offset << "\n"
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<< "<--------->\n");
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unsigned Reg = MI.getOperand(0).getReg();
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assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand");
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if (!TFI->hasFP(MF)) {
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Offset = StackSize + Offset;
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if (FrameIndex >= 0)
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assert((Offset >= 0 && Offset < StackSize) && "SP Offset not in bounds.");
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} else {
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if (FrameIndex >= 0) {
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assert((Offset < 0 && -Offset <= StackSize) &&
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"FP Offset not in bounds.");
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}
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}
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ReplaceFrameIndex(II, TII, Reg, getFrameRegister(MF), Offset, StackSize,
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ObjSize, RS, SPAdj);
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}
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unsigned ARCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const ARCFrameLowering *TFI = getFrameLowering(MF);
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return TFI->hasFP(MF) ? ARC::FP : ARC::SP;
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}
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const uint32_t *
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ARCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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return CSR_ARC_RegMask;
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}
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