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Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a🅱️c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
203 lines
5.1 KiB
LLVM
203 lines
5.1 KiB
LLVM
; RUN: llc < %s -march=arm64 | FileCheck %s
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;==--------------------------------------------------------------------------==
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; Tests for MOV-immediate implemented with ORR-immediate.
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;==--------------------------------------------------------------------------==
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; 64-bit immed with 32-bit pattern size, rotated by 0.
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define i64 @test64_32_rot0() nounwind {
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; CHECK-LABEL: test64_32_rot0:
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; CHECK: orr x0, xzr, #0x700000007
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ret i64 30064771079
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}
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; 64-bit immed with 32-bit pattern size, rotated by 2.
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define i64 @test64_32_rot2() nounwind {
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; CHECK-LABEL: test64_32_rot2:
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; CHECK: orr x0, xzr, #0xc0000003c0000003
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ret i64 13835058071388291075
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}
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; 64-bit immed with 4-bit pattern size, rotated by 3.
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define i64 @test64_4_rot3() nounwind {
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; CHECK-LABEL: test64_4_rot3:
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; CHECK: orr x0, xzr, #0xeeeeeeeeeeeeeeee
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ret i64 17216961135462248174
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}
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; 32-bit immed with 32-bit pattern size, rotated by 16.
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define i32 @test32_32_rot16() nounwind {
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; CHECK-LABEL: test32_32_rot16:
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; CHECK: orr w0, wzr, #0xff0000
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ret i32 16711680
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}
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; 32-bit immed with 2-bit pattern size, rotated by 1.
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define i32 @test32_2_rot1() nounwind {
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; CHECK-LABEL: test32_2_rot1:
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; CHECK: orr w0, wzr, #0xaaaaaaaa
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ret i32 2863311530
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}
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;==--------------------------------------------------------------------------==
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; Tests for MOVZ with MOVK.
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;==--------------------------------------------------------------------------==
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define i32 @movz() nounwind {
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; CHECK-LABEL: movz:
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; CHECK: movz w0, #5
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ret i32 5
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}
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define i64 @movz_3movk() nounwind {
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; CHECK-LABEL: movz_3movk:
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; CHECK: movz x0, #5, lsl #48
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; CHECK-NEXT: movk x0, #4660, lsl #32
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; CHECK-NEXT: movk x0, #43981, lsl #16
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; CHECK-NEXT: movk x0, #22136
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ret i64 1427392313513592
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}
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define i64 @movz_movk_skip1() nounwind {
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; CHECK-LABEL: movz_movk_skip1:
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; CHECK: movz x0, #5, lsl #32
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; CHECK-NEXT: movk x0, #17185, lsl #16
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ret i64 22601072640
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}
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define i64 @movz_skip1_movk() nounwind {
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; CHECK-LABEL: movz_skip1_movk:
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; CHECK: movz x0, #34388, lsl #32
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; CHECK-NEXT: movk x0, #4660
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ret i64 147695335379508
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}
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;==--------------------------------------------------------------------------==
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; Tests for MOVN with MOVK.
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;==--------------------------------------------------------------------------==
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define i64 @movn() nounwind {
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; CHECK-LABEL: movn:
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; CHECK: movn x0, #41
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ret i64 -42
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}
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define i64 @movn_skip1_movk() nounwind {
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; CHECK-LABEL: movn_skip1_movk:
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; CHECK: movn x0, #41, lsl #32
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; CHECK-NEXT: movk x0, #4660
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ret i64 -176093720012
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}
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;==--------------------------------------------------------------------------==
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; Tests for ORR with MOVK.
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;==--------------------------------------------------------------------------==
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; rdar://14987673
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define i64 @orr_movk1() nounwind {
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; CHECK-LABEL: orr_movk1:
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; CHECK: orr x0, xzr, #0xffff0000ffff0
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; CHECK: movk x0, #57005, lsl #16
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ret i64 72056498262245120
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}
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define i64 @orr_movk2() nounwind {
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; CHECK-LABEL: orr_movk2:
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; CHECK: orr x0, xzr, #0xffff0000ffff0
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; CHECK: movk x0, #57005, lsl #48
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ret i64 -2400982650836746496
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}
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define i64 @orr_movk3() nounwind {
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; CHECK-LABEL: orr_movk3:
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; CHECK: orr x0, xzr, #0xffff0000ffff0
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; CHECK: movk x0, #57005, lsl #32
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ret i64 72020953688702720
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}
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define i64 @orr_movk4() nounwind {
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; CHECK-LABEL: orr_movk4:
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; CHECK: orr x0, xzr, #0xffff0000ffff0
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; CHECK: movk x0, #57005
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ret i64 72056494543068845
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}
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; rdar://14987618
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define i64 @orr_movk5() nounwind {
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; CHECK-LABEL: orr_movk5:
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; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
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; CHECK: movk x0, #57005, lsl #16
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ret i64 -71777214836900096
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}
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define i64 @orr_movk6() nounwind {
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; CHECK-LABEL: orr_movk6:
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; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
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; CHECK: movk x0, #57005, lsl #16
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; CHECK: movk x0, #57005, lsl #48
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ret i64 -2400982647117578496
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}
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define i64 @orr_movk7() nounwind {
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; CHECK-LABEL: orr_movk7:
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; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
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; CHECK: movk x0, #57005, lsl #48
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ret i64 -2400982646575268096
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}
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define i64 @orr_movk8() nounwind {
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; CHECK-LABEL: orr_movk8:
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; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
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; CHECK: movk x0, #57005
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; CHECK: movk x0, #57005, lsl #48
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ret i64 -2400982646575276371
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}
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; rdar://14987715
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define i64 @orr_movk9() nounwind {
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; CHECK-LABEL: orr_movk9:
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; CHECK: orr x0, xzr, #0xffffff000000000
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; CHECK: movk x0, #65280
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; CHECK: movk x0, #57005, lsl #16
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ret i64 1152921439623315200
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}
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define i64 @orr_movk10() nounwind {
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; CHECK-LABEL: orr_movk10:
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; CHECK: orr x0, xzr, #0xfffffffffffff00
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; CHECK: movk x0, #57005, lsl #16
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ret i64 1152921504047824640
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}
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define i64 @orr_movk11() nounwind {
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; CHECK-LABEL: orr_movk11:
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; CHECK: orr x0, xzr, #0xfff00000000000ff
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; CHECK: movk x0, #57005, lsl #16
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; CHECK: movk x0, #65535, lsl #32
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ret i64 -4222125209747201
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}
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define i64 @orr_movk12() nounwind {
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; CHECK-LABEL: orr_movk12:
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; CHECK: orr x0, xzr, #0xfff00000000000ff
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; CHECK: movk x0, #57005, lsl #32
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ret i64 -4258765016661761
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}
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define i64 @orr_movk13() nounwind {
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; CHECK-LABEL: orr_movk13:
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; CHECK: orr x0, xzr, #0xfffff000000
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; CHECK: movk x0, #57005
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; CHECK: movk x0, #57005, lsl #48
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ret i64 -2401245434149282131
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}
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; rdar://13944082
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define i64 @g() nounwind {
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; CHECK-LABEL: g:
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; CHECK: movz x0, #65535, lsl #48
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; CHECK: movk x0, #2
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entry:
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ret i64 -281474976710654
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}
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