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Most of the time ARM has the CCR.UNALIGN_TRP bit set to false which means that unaligned loads/stores do not trap and even extensive testing will not catch these bugs. However the multi/double variants are not affected by this bit and will still trap. In effect a more aggressive load/store optimization will break existing (bad) code. These bugs do not necessarily manifest in the broken code where the misaligned pointer is formed but often later in perfectly legal code where it is accessed. This means recompiling system libraries (which have no alignment bugs) with a newer compiler will break existing applications (with alignment bugs) that worked before. So (under protest) I implemented this safe mode which limits the formation of multi/double operations to cases that are not affected by user code (stack operations like spills/reloads) or cases where the normal operations trap anyway (floating point load/stores). It is disabled by default. Differential Revision: http://reviews.llvm.org/D17015 llvm-svn: 262504
31 lines
1.3 KiB
LLVM
31 lines
1.3 KiB
LLVM
; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s
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; RUN: llc < %s -arm-assume-misaligned-load-store -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s
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; Check that we avoid producing vldm instructions using d registers that
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; begin in the most-significant half of a q register. These require more
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; micro-ops on swift and so aren't worth combining.
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; CHECK-LABEL: test_vldm
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; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}
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; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4}
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declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
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define void @test_vldm(double* %x, double * %y) {
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entry:
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%addr1 = getelementptr double, double * %x, i32 1
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%addr2 = getelementptr double, double * %x, i32 2
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%addr3 = getelementptr double, double * %x, i32 3
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%d0 = load double , double * %y
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%d1 = load double , double * %x
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%d2 = load double , double * %addr1
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%d3 = load double , double * %addr2
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%d4 = load double , double * %addr3
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; We are trying to force x[0-3] in registers d1 to d4 so that we can test we
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; don't form a "vldmia rX, {d1, d2, d3, d4}".
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; We are relying on the calling convention and that register allocation
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; properly coalesces registers.
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call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
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ret void
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}
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