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852aec9243
When we see a SETCC whose only users are zero extend operations, we can replace it with a subtraction. This results in doing all calculations in GPRs and avoids CR use. Currently we do this only for ULT, ULE, UGT and UGE condition codes. There are ways that this can be extended. For example for signed condition codes. In that case we will be introducing additional sign extend instructions, so more careful profitability analysis may be required. Another direction to extend this is for equal, not equal conditions. Also when users of SETCC are any_ext or sign_ext, we might be able to do something similar. llvm-svn: 287329
97 lines
3.0 KiB
LLVM
97 lines
3.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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%class.PB2 = type { [1 x i32], %class.PB1* }
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%class.PB1 = type { [1 x i32], i64, i64, i32 }
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; Function Attrs: norecurse nounwind readonly
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define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
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entry:
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%arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
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%0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
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%and.i = and i32 %0, 8
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%arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
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%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
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%and.i4 = and i32 %1, 8
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%cmp.i5 = icmp ult i32 %and.i, %and.i4
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ret i1 %cmp.i5
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; CHECK-LABEL: @test1
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; CHECK: rlwinm [[REG1:[0-9]*]]
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; CHECK-NEXT: rlwinm [[REG2:[0-9]*]]
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; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG1]], [[REG2]]
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; CHECK-NEXT: rldicl 3, [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readonly
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define zeroext i1 @test2(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
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entry:
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%arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
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%0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
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%and.i = and i32 %0, 8
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%arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
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%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
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%and.i4 = and i32 %1, 8
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%cmp.i5 = icmp ule i32 %and.i, %and.i4
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ret i1 %cmp.i5
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; CHECK-LABEL: @test2
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; CHECK: rlwinm [[REG1:[0-9]*]]
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; CHECK-NEXT: rlwinm [[REG2:[0-9]*]]
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; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG2]], [[REG1]]
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; CHECK-NEXT: rldicl [[REG4:[0-9]*]], [[REG3]]
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; CHECK-NEXT: xori 3, [[REG4]], 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readonly
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define zeroext i1 @test3(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
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entry:
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%arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
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%0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
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%and.i = and i32 %0, 8
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%arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
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%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
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%and.i4 = and i32 %1, 8
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%cmp.i5 = icmp ugt i32 %and.i, %and.i4
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ret i1 %cmp.i5
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; CHECK-LABEL: @test3
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; CHECK: rlwinm [[REG1:[0-9]*]]
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; CHECK-NEXT: rlwinm [[REG2:[0-9]*]]
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; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG2]], [[REG1]]
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; CHECK-NEXT: rldicl 3, [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readonly
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define zeroext i1 @test4(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
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entry:
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%arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
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%0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
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%and.i = and i32 %0, 8
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%arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
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%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
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%and.i4 = and i32 %1, 8
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%cmp.i5 = icmp uge i32 %and.i, %and.i4
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ret i1 %cmp.i5
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; CHECK-LABEL: @test4
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; CHECK: rlwinm [[REG1:[0-9]*]]
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; CHECK-NEXT: rlwinm [[REG2:[0-9]*]]
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; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG1]], [[REG2]]
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; CHECK-NEXT: rldicl [[REG4:[0-9]*]], [[REG3]]
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; CHECK-NEXT: xori 3, [[REG4]], 1
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; CHECK: blr
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}
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C++ TBAA"}
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