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7ebfc5f86b
This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
65 lines
2.1 KiB
LLVM
65 lines
2.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-P9 \
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; RUN: --implicit-check-not xxswapd
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -verify-machineinstrs -mattr=-power9-vector < %s | FileCheck %s
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; These tests verify that VSX swap optimization works when loading a scalar
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; into a vector register.
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@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
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@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
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@y = global double 1.780000e+00, align 8
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define void @bar0() {
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 0
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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; CHECK-LABEL: @bar0
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; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
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; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
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; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
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; CHECK: xxpermdi [[REG5:[0-9]+]], [[REG4]], [[REG1]], 1
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; CHECK: stxvd2x [[REG5]]
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; CHECK-P9-LABEL: @bar0
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; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]]
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; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3)
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; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
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; CHECK-P9: xxpermdi [[REG5:[0-9]+]], [[REG1]], [[REG4]], 1
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; CHECK-P9: stxvx [[REG5]]
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define void @bar1() {
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 1
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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; CHECK-LABEL: @bar1
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; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
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; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
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; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
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; CHECK: xxmrghd [[REG5:[0-9]+]], [[REG1]], [[REG4]]
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; CHECK: stxvd2x [[REG5]]
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; CHECK-P9-LABEL: @bar1
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; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]]
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; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3)
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; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
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; CHECK-P9: xxmrgld [[REG5:[0-9]+]], [[REG4]], [[REG1]]
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; CHECK-P9: stxvx [[REG5]]
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