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db43217a24
Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
63 lines
2.0 KiB
LLVM
63 lines
2.0 KiB
LLVM
; Check VMX 64-bit integer operations
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;
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
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define <2 x i64> @test_add(<2 x i64> %x, <2 x i64> %y) nounwind {
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%result = add <2 x i64> %x, %y
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ret <2 x i64> %result
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; CHECK: vaddudm 2, 2, 3
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}
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define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind {
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%result = add <2 x i64> %x, <i64 1, i64 1>
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ret <2 x i64> %result
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; CHECK: vaddudm 2, 2, 3
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}
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define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {
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%tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0
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%tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1
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%result = add <2 x i64> %x, %tmpvec2
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ret <2 x i64> %result
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; CHECK: vaddudm 2, 2, 3
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; FIXME: This is currently generating the following instruction sequence
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;
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; std 5, -8(1)
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; std 5, -16(1)
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; addi 3, 1, -16
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; ori 2, 2, 0
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; lxvd2x 35, 0, 3
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; vaddudm 2, 2, 3
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; blr
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;
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; This will almost certainly cause a load-hit-store hazard.
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; Since val is a value parameter, it should not need to be
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; saved onto the stack at all (unless we're using this to set
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; up the vector register). Instead, it would be better to splat
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; the value into a vector register.
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}
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define <2 x i64> @test_sub(<2 x i64> %x, <2 x i64> %y) nounwind {
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%result = sub <2 x i64> %x, %y
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ret <2 x i64> %result
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; CHECK: vsubudm 2, 2, 3
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}
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define <2 x i64> @decrement_by_one(<2 x i64> %x) nounwind {
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%result = sub <2 x i64> %x, <i64 -1, i64 -1>
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ret <2 x i64> %result
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; CHECK: vsubudm 2, 2, 3
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}
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define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind {
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%tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0
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%tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1
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%result = sub <2 x i64> %x, %tmpvec2
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ret <2 x i64> %result
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; CHECK: vsubudm 2, 2, 3
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}
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