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048a920e0e
Summary: The goal is for each operand type to have its own parse function and at the same time share common code for tracking state as different instruction types share operand types (e.g. glc/glc_flat, etc). Introduce parseAMDGPUOperand which can parse any optional operand. DPP and Clamp/OMod have custom handling for now. Sam also suggested to have class hierarchy for operand types instead of table. This can be done in separate change. Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps, parseMubufOptionalOps, parseDPPOptionalOps. Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class. Rename AsmMatcher/InstPrinter methods accordingly. Print immediate type when printing parsed immediate operand. Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3). Update tests. Reviewers: tstellarAMD, SamWot, artem.tamazov Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19584 llvm-svn: 268015
39 lines
1.6 KiB
LLVM
39 lines
1.6 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}reduce_i64_load_align_4_width_to_i32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, [[VAL]]
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; GCN: buffer_store_dwordx2
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define void @reduce_i64_load_align_4_width_to_i32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #0 {
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%a = load i64, i64 addrspace(1)* %in, align 4
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%and = and i64 %a, 1234567
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}reduce_i64_align_4_bitcast_v2i32_elt0:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN: buffer_store_dword [[VAL]]
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define void @reduce_i64_align_4_bitcast_v2i32_elt0(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #0 {
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%a = load i64, i64 addrspace(1)* %in, align 4
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%vec = bitcast i64 %a to <2 x i32>
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%elt0 = extractelement <2 x i32> %vec, i32 0
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store i32 %elt0, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}reduce_i64_align_4_bitcast_v2i32_elt1:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4
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; GCN: buffer_store_dword [[VAL]]
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define void @reduce_i64_align_4_bitcast_v2i32_elt1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #0 {
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%a = load i64, i64 addrspace(1)* %in, align 4
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%vec = bitcast i64 %a to <2 x i32>
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%elt0 = extractelement <2 x i32> %vec, i32 1
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store i32 %elt0, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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