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eed028bbcd
This was meant to be part of SVN r267080. cbz cannot use a high register, which would be silently truncated. This has now been fixed. llvm-svn: 267092
54 lines
1.1 KiB
LLVM
54 lines
1.1 KiB
LLVM
; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
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; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s
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define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) {
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entry:
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%div = sdiv i32 %divident, %divisor
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ret i32 %div
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}
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; CHECK-LABEL: sdiv32:
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; CHECK: cbz r0
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; CHECK: b
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; CHECK: udf.w #249
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; CHECK: bl __rt_sdiv
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define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
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entry:
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%div = udiv i32 %divident, %divisor
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ret i32 %div
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}
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; CHECK-LABEL: udiv32:
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; CHECK: cbz r0
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; CHECK: b
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; CHECK: udf.w #249
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; CHECK: bl __rt_udiv
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define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
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entry:
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%div = sdiv i64 %divident, %divisor
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ret i64 %div
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}
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; CHECK-LABEL: sdiv64:
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; CHECK: orr.w r4, r0, r1
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; CHECK-NEXT: cbz r4
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; CHECK: b
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; CHECK: udf.w #249
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; CHECK: bl __rt_sdiv64
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define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
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entry:
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%div = udiv i64 %divident, %divisor
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ret i64 %div
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}
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; CHECK-LABEL: udiv64:
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; CHECK: orr.w r4, r0, r1
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; CHECK-NEXT: cbz r4
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; CHECK: b
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; CHECK: udf.w #249
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; CHECK: bl __rt_udiv64
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