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51 lines
1.8 KiB
LLVM
51 lines
1.8 KiB
LLVM
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \
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; RUN: -relocation-model=pic < %s | \
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; RUN: FileCheck %s -check-prefixes=ALL,MM32
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; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \
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; RUN: -relocation-model=pic < %s | \
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; RUN: FileCheck %s -check-prefixes=ALL,MM32
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; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \
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; RUN: -relocation-model=pic < %s | \
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; RUN: FileCheck %s -check-prefixes=ALL,MM64
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@gf0 = external global float
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define float @test_lwc1() {
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entry:
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; CHECK-LABEL: test_lwc1
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; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp)
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; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
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; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25
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; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]])
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; MM32: lwc1 $f0, 0($[[R3]])
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; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1)))
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; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25
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; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1)))
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; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
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; MM64: lwc1 $f0, 0($[[R3]])
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%0 = load float, float* @gf0, align 4
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ret float %0
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}
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define void @test_swc1(float %a) {
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entry:
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; CHECK-LABEL: test_swc1
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; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp)
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; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
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; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25
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; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]])
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; MM32: swc1 $f12, 0($[[R3]])
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; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1)))
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; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25
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; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1)))
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; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
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; MM64: swc1 $f12, 0($[[R3]])
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store float %a, float* @gf0, align 4
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ret void
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}
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