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https://github.com/RPCS3/llvm-mirror.git
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25efe2087b
llvm-svn: 55014
125 lines
4.0 KiB
C++
125 lines
4.0 KiB
C++
///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the FastISel class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Instructions.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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BasicBlock::iterator
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FastISel::SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
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DenseMap<const Value*, unsigned> &ValueMap) {
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BasicBlock::iterator I = Begin;
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for (; I != End; ++I) {
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switch (I->getOpcode()) {
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case Instruction::Add: {
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unsigned Op0 = ValueMap[I->getOperand(0)];
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unsigned Op1 = ValueMap[I->getOperand(1)];
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple()) {
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// Unhandled type. Halt "fast" selection and bail.
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return I;
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}
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unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISD::ADD, Op0, Op1);
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if (ResultReg == 0) {
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// Target-specific code wasn't able to find a machine opcode for
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// the given ISD opcode and type. Halt "fast" selection and bail.
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return I;
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}
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ValueMap[I] = ResultReg;
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break;
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}
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case Instruction::Br: {
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BranchInst *BI = cast<BranchInst>(I);
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// For now, check for and handle just the most trivial case: an
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// unconditional fall-through branch.
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if (BI->isUnconditional() &&
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next(MachineFunction::iterator(MBB))->getBasicBlock() ==
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BI->getSuccessor(0)) {
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MBB->addSuccessor(next(MachineFunction::iterator(MBB)));
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break;
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}
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// Something more complicated. Halt "fast" selection and bail.
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return I;
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}
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default:
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// Unhandled instruction. Halt "fast" selection and bail.
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return I;
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}
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}
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return I;
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}
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FastISel::~FastISel() {}
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unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
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return 0;
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}
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unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
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unsigned /*Op0*/) {
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return 0;
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}
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unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
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unsigned /*Op0*/, unsigned /*Op0*/) {
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return 0;
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}
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unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass* RC) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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MBB->push_back(MI);
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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MI->addOperand(MachineOperand::CreateReg(Op0, false));
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MBB->push_back(MI);
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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MI->addOperand(MachineOperand::CreateReg(Op0, false));
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MI->addOperand(MachineOperand::CreateReg(Op1, false));
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MBB->push_back(MI);
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return ResultReg;
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}
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