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e5fbe2c41d
Summary:
In LLVM, 't' selects a floating-point/SIMD register and only supports
32-bit values. This is appropriately documented in the LLVM Language
Reference Manual. However, this behaviour diverges from that of GCC, where
't' selects the s0-s31 registers and its qX and dX variants depending on
additional operand modifiers (q/P).
For example, the following C code:
#include <arm_neon.h>
float32x4_t a, b, x;
asm("vadd.f32 %0, %1, %2" : "=t" (x) : "t" (a), "t" (b))
results in the following assembly if compiled with GCC:
vadd.f32 s0, s0, s1
whereas LLVM will show "error: couldn't allocate output register for
constraint 't'", since a, b, x are 128-bit variables, not 32-bit.
This patch extends the use of 't' to mean that of GCC, thus allowing
selection of the lower Q vector regs and their D/S variants. For example,
the earlier code will now compile as:
vadd.f32 q0, q0, q1
This behaviour still differs from that of GCC but I think it is actually
more correct, since LLVM picks up the right register type based on the
datatype of x, while GCC would need an extra operand modifier to achieve
the same result, as follows:
asm("vadd.f32 %q0, %q1, %q2" : "=t" (x) : "t" (a), "t" (b))
Since this is only an extension of functionality, existing code should not
be affected by this change. Note that operand modifiers q/P are already
supported by LLVM, so this patch should suffice to support inline
assembly with constraint 't' originally built for GCC.
Reviewers: grosbach, rengolin
Reviewed By: rengolin
Subscribers: rogfer01, efriedma, olista01, aemerson, javed.absar, eraman, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D42962
llvm-svn: 325244
51 lines
1.6 KiB
LLVM
51 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=armv8-eabi -mattr=+neon %s -o - | FileCheck %s
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define i32 @test1(i32 %tmp54) {
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%tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 ) ; <i32> [#uses=1]
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ret i32 %tmp56
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}
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define void @test2() {
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tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
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ret void
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}
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define float @t-constraint-int(i32 %i) {
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; CHECK-LABEL: t-constraint-int
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; CHECK: vcvt.f32.s32 {{s[0-9]+}}, {{s[0-9]+}}
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%ret = call float asm "vcvt.f32.s32 $0, $1\0A", "=t,t"(i32 %i)
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ret float %ret
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}
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define <2 x i32> @t-constraint-int-vector-64bit(<2 x float> %x) {
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entry:
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; CHECK-LABEL: t-constraint-int-vector-64bit
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; CHECK: vcvt.s32.f32 {{d[0-9]+}}, {{d[0-9]+}}
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%0 = tail call <2 x i32> asm "vcvt.s32.f32 $0, $1", "=t,t"(<2 x float> %x)
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ret <2 x i32> %0
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}
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define <4 x i32> @t-constraint-int-vector-128bit(<4 x float> %x) {
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entry:
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; CHECK-LABEL: t-constraint-int-vector-128bit
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; CHECK: vcvt.s32.f32 {{q[0-7]}}, {{q[0-7]}}
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%0 = tail call <4 x i32> asm "vcvt.s32.f32 $0, $1", "=t,t"(<4 x float> %x)
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ret <4 x i32> %0
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}
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define <2 x float> @t-constraint-float-vector-64bit(<2 x float> %a, <2 x float> %b) {
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entry:
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; CHECK-LABEL: t-constraint-float-vector-64bit
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; CHECK: vadd.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%0 = tail call <2 x float> asm "vadd.f32 $0, $1, $2", "=t,t,t"(<2 x float> %a, <2 x float> %b)
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ret <2 x float> %0
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}
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define <4 x float> @t-constraint-float-vector-128bit(<4 x float> %a, <4 x float> %b) {
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entry:
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; CHECK-LABEL: t-constraint-float-vector-128bit
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; CHECK: vadd.f32 q{{[0-7]}}, q{{[0-7]}}, q{{[0-7]}}
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%0 = tail call <4 x float> asm "vadd.f32 $0, $1, $2", "=t,t,t"(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %0
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}
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