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2ea054f685
This is a redo of r251849 except the tests have been split into arch-specific folders to hopefully make the bots happy. This is a follow-up from the discussion in D12965. The block-at-a-time limitation of SelectionDAG also came up in D13297. Without the InstCombine change from D12965, I don't expect this patch to make any difference in the real world because InstCombine does not shrink cases like this in visitSwitchInst(). But we need to have this CGP safety harness in place before proceeding with any shrinkage in D12965, so we won't generate extra extends for compares. I've opted for IR regression tests in the patch because that seems like a clearer way to test the transform, but PowerPC CodeGen for an i16 widening test is shown below. x86 will need more work to solve: https://llvm.org/bugs/show_bug.cgi?id=22473 Before: BB#0: mr 4, 3 extsh. 3, 4 ble 0, .LBB0_5 BB#1: cmpwi 3, 99 bgt 0, .LBB0_9 BB#2: rlwinm 4, 4, 0, 16, 31 <--- 32-bit mask/extend li 3, 0 cmplwi 4, 1 beqlr 0 BB#3: cmplwi 4, 10 bne 0, .LBB0_12 BB#4: li 3, 1 blr .LBB0_5: rlwinm 3, 4, 0, 16, 31 <--- 32-bit mask/extend cmplwi 3, 65436 beq 0, .LBB0_13 BB#6: cmplwi 3, 65526 beq 0, .LBB0_15 BB#7: cmplwi 3, 65535 bne 0, .LBB0_12 BB#8: li 3, 4 blr .LBB0_9: rlwinm 3, 4, 0, 16, 31 <--- 32-bit mask/extend cmplwi 3, 100 beq 0, .LBB0_14 ... After: BB#0: rlwinm 4, 3, 0, 16, 31 <--- mask/extend to 32-bit and then use that for comparisons cmpwi 4, 999 ble 0, .LBB0_5 BB#1: lis 3, 0 ori 3, 3, 65525 cmpw 4, 3 bgt 0, .LBB0_9 BB#2: cmplwi 4, 1000 beq 0, .LBB0_14 BB#3: cmplwi 4, 65436 bne 0, .LBB0_13 BB#4: li 3, 6 blr .LBB0_5: li 3, 0 cmplwi 4, 1 beqlr 0 BB#6: cmplwi 4, 10 beq 0, .LBB0_12 BB#7: cmplwi 4, 100 bne 0, .LBB0_13 BB#8: li 3, 2 blr .LBB0_9: cmplwi 4, 65526 beq 0, .LBB0_15 BB#10: cmplwi 4, 65535 bne 0, .LBB0_13 ... Differential Revision: http://reviews.llvm.org/D13532 llvm-svn: 251857
96 lines
2.1 KiB
LLVM
96 lines
2.1 KiB
LLVM
;; AArch64 is arbitralily chosen as a 32/64-bit RISC representative to show the transform in all tests.
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; RUN: opt < %s -codegenprepare -S -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefix=ARM64
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; AArch64 widens to 32-bit.
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define i32 @widen_switch_i16(i32 %a) {
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entry:
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%trunc = trunc i32 %a to i16
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switch i16 %trunc, label %sw.default [
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i16 1, label %sw.bb0
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i16 -1, label %sw.bb1
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]
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sw.bb0:
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br label %return
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sw.bb1:
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br label %return
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sw.default:
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br label %return
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return:
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%retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
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ret i32 %retval
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; ARM64-LABEL: @widen_switch_i16(
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; ARM64: %0 = zext i16 %trunc to i32
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; ARM64-NEXT: switch i32 %0, label %sw.default [
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; ARM64-NEXT: i32 1, label %return
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; ARM64-NEXT: i32 65535, label %sw.bb1
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}
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; Widen to 32-bit from a smaller, non-native type.
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define i32 @widen_switch_i17(i32 %a) {
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entry:
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%trunc = trunc i32 %a to i17
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switch i17 %trunc, label %sw.default [
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i17 10, label %sw.bb0
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i17 -1, label %sw.bb1
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]
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sw.bb0:
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br label %return
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sw.bb1:
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br label %return
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sw.default:
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br label %return
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return:
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%retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
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ret i32 %retval
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; ARM64-LABEL: @widen_switch_i17(
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; ARM64: %0 = zext i17 %trunc to i32
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; ARM64-NEXT: switch i32 %0, label %sw.default [
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; ARM64-NEXT: i32 10, label %return
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; ARM64-NEXT: i32 131071, label %sw.bb1
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}
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; If the switch condition is a sign-extended function argument, then the
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; condition and cases should be sign-extended rather than zero-extended
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; because the sign-extension can be optimized away.
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define i32 @widen_switch_i16_sext(i2 signext %a) {
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entry:
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switch i2 %a, label %sw.default [
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i2 1, label %sw.bb0
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i2 -1, label %sw.bb1
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]
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sw.bb0:
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br label %return
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sw.bb1:
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br label %return
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sw.default:
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br label %return
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return:
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%retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
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ret i32 %retval
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; ARM64-LABEL: @widen_switch_i16_sext(
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; ARM64: %0 = sext i2 %a to i32
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; ARM64-NEXT: switch i32 %0, label %sw.default [
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; ARM64-NEXT: i32 1, label %return
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; ARM64-NEXT: i32 -1, label %sw.bb1
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}
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