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f403d95eb4
This patch provides initial implementation of load address
macro instruction for Mips. We have implemented two kinds
of expansions with their variations depending on the size
of immediate operand:
1) load address with immediate value directly:
* la d,j => addiu d,$zero,j (for -32768 <= j <= 65535)
* la d,j => lui d,hi16(j)
ori d,d,lo16(j) (for any other 32 bit value of j)
2) load load address with register offset value
* la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535)
* la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j)
ori d,d,lo16(j)
addu d,d,s
This patch does not cover the case when the address is loaded
from the value of the label or function.
Contributer: Vladimir Medic
llvm-svn: 165561
28 lines
1.3 KiB
ArmAsm
28 lines
1.3 KiB
ArmAsm
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
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# Check that the assembler can handle the documented syntax
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# for macro instructions
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# CHECK: .section __TEXT,__text,regular,pure_instructions
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#------------------------------------------------------------------------------
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# Load immediate instructions
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#------------------------------------------------------------------------------
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# CHECK: ori $5, $zero, 123 # encoding: [0x7b,0x00,0x05,0x34]
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# CHECK: addiu $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24]
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# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
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# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
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# CHECK: addiu $4, $zero, 20 # encoding: [0x14,0x00,0x04,0x24]
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# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
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# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
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# CHECK: addiu $4, $5, 20 # encoding: [0x14,0x00,0xa4,0x24]
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# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
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# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
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# CHECK: addu $7, $7, $8 # encoding: [0x21,0x38,0xe8,0x00]
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li $5,123
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li $6,-2345
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li $7,65538
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la $a0, 20
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la $7,65538
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la $a0, 20($a1)
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la $7,65538($8)
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