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ea36e0a92b
We want to have more load/store clustering but we also want to maintain low register pressure which are oposit targets. Allow scheduler to reschedule regions without mutations applied if we hit a register limit. Differential Revision: https://reviews.llvm.org/D73386
130 lines
3.8 KiB
C++
130 lines
3.8 KiB
C++
//===-- GCNSchedStrategy.h - GCN Scheduler Strategy -*- C++ -*-------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
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#define LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
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#include "GCNRegPressure.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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namespace llvm {
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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class GCNSubtarget;
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/// This is a minimal scheduler strategy. The main difference between this
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/// and the GenericScheduler is that GCNSchedStrategy uses different
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/// heuristics to determine excess/critical pressure sets. Its goal is to
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/// maximize kernel occupancy (i.e. maximum number of waves per simd).
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class GCNMaxOccupancySchedStrategy final : public GenericScheduler {
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friend class GCNScheduleDAGMILive;
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SUnit *pickNodeBidirectional(bool &IsTopNode);
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void pickNodeFromQueue(SchedBoundary &Zone, const CandPolicy &ZonePolicy,
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const RegPressureTracker &RPTracker,
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SchedCandidate &Cand);
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void initCandidate(SchedCandidate &Cand, SUnit *SU,
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bool AtTop, const RegPressureTracker &RPTracker,
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const SIRegisterInfo *SRI,
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unsigned SGPRPressure, unsigned VGPRPressure);
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std::vector<unsigned> Pressure;
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std::vector<unsigned> MaxPressure;
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unsigned SGPRExcessLimit;
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unsigned VGPRExcessLimit;
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unsigned SGPRCriticalLimit;
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unsigned VGPRCriticalLimit;
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unsigned TargetOccupancy;
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MachineFunction *MF;
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public:
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GCNMaxOccupancySchedStrategy(const MachineSchedContext *C);
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SUnit *pickNode(bool &IsTopNode) override;
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void initialize(ScheduleDAGMI *DAG) override;
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void setTargetOccupancy(unsigned Occ) { TargetOccupancy = Occ; }
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};
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class GCNScheduleDAGMILive final : public ScheduleDAGMILive {
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enum : unsigned {
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Collect,
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InitialSchedule,
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UnclusteredReschedule,
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ClusteredLowOccupancyReschedule,
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LastStage = ClusteredLowOccupancyReschedule
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};
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const GCNSubtarget &ST;
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SIMachineFunctionInfo &MFI;
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// Occupancy target at the beginning of function scheduling cycle.
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unsigned StartingOccupancy;
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// Minimal real occupancy recorder for the function.
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unsigned MinOccupancy;
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// Scheduling stage number.
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unsigned Stage;
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// Current region index.
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size_t RegionIdx;
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// Vector of regions recorder for later rescheduling
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SmallVector<std::pair<MachineBasicBlock::iterator,
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MachineBasicBlock::iterator>, 32> Regions;
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// Records if a region is not yet scheduled, or schedule has been reverted,
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// or we generally desire to reschedule it.
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BitVector RescheduleRegions;
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// Region live-in cache.
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SmallVector<GCNRPTracker::LiveRegSet, 32> LiveIns;
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// Region pressure cache.
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SmallVector<GCNRegPressure, 32> Pressure;
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// Temporary basic block live-in cache.
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DenseMap<const MachineBasicBlock*, GCNRPTracker::LiveRegSet> MBBLiveIns;
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DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet> BBLiveInMap;
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DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet> getBBLiveInMap() const;
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// Return current region pressure.
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GCNRegPressure getRealRegPressure() const;
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// Compute and cache live-ins and pressure for all regions in block.
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void computeBlockPressure(const MachineBasicBlock *MBB);
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public:
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GCNScheduleDAGMILive(MachineSchedContext *C,
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std::unique_ptr<MachineSchedStrategy> S);
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void schedule() override;
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void finalizeSchedule() override;
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};
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} // End namespace llvm
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#endif // GCNSCHEDSTRATEGY_H
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