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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
171 lines
4.2 KiB
C++
171 lines
4.2 KiB
C++
//===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
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#define LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
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#include "llvm/MC/MCRegisterInfo.h"
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// Operand Flags
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#define MO_FLAG_CLAMP (1 << 0)
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#define MO_FLAG_NEG (1 << 1)
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#define MO_FLAG_ABS (1 << 2)
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#define MO_FLAG_MASK (1 << 3)
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#define MO_FLAG_PUSH (1 << 4)
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#define MO_FLAG_NOT_LAST (1 << 5)
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#define MO_FLAG_LAST (1 << 6)
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#define NUM_MO_FLAGS 7
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/// Helper for getting the operand index for the instruction flags
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/// operand.
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#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
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namespace R600_InstFlag {
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enum TIF {
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TRANS_ONLY = (1 << 0),
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TEX = (1 << 1),
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REDUCTION = (1 << 2),
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FC = (1 << 3),
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TRIG = (1 << 4),
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OP3 = (1 << 5),
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VECTOR = (1 << 6),
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//FlagOperand bits 7, 8
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NATIVE_OPERANDS = (1 << 9),
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OP1 = (1 << 10),
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OP2 = (1 << 11),
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VTX_INST = (1 << 12),
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TEX_INST = (1 << 13),
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ALU_INST = (1 << 14),
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LDS_1A = (1 << 15),
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LDS_1A1D = (1 << 16),
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IS_EXPORT = (1 << 17),
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LDS_1A2D = (1 << 18)
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};
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}
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#define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
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/// Defines for extracting register information from register encoding
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#define HW_REG_MASK 0x1ff
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#define HW_CHAN_SHIFT 9
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#define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
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#define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
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#define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
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#define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
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namespace OpName {
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enum VecOps {
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UPDATE_EXEC_MASK_X,
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UPDATE_PREDICATE_X,
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WRITE_X,
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OMOD_X,
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DST_REL_X,
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CLAMP_X,
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SRC0_X,
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SRC0_NEG_X,
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SRC0_REL_X,
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SRC0_ABS_X,
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SRC0_SEL_X,
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SRC1_X,
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SRC1_NEG_X,
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SRC1_REL_X,
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SRC1_ABS_X,
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SRC1_SEL_X,
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PRED_SEL_X,
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UPDATE_EXEC_MASK_Y,
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UPDATE_PREDICATE_Y,
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WRITE_Y,
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OMOD_Y,
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DST_REL_Y,
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CLAMP_Y,
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SRC0_Y,
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SRC0_NEG_Y,
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SRC0_REL_Y,
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SRC0_ABS_Y,
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SRC0_SEL_Y,
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SRC1_Y,
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SRC1_NEG_Y,
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SRC1_REL_Y,
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SRC1_ABS_Y,
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SRC1_SEL_Y,
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PRED_SEL_Y,
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UPDATE_EXEC_MASK_Z,
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UPDATE_PREDICATE_Z,
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WRITE_Z,
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OMOD_Z,
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DST_REL_Z,
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CLAMP_Z,
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SRC0_Z,
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SRC0_NEG_Z,
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SRC0_REL_Z,
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SRC0_ABS_Z,
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SRC0_SEL_Z,
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SRC1_Z,
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SRC1_NEG_Z,
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SRC1_REL_Z,
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SRC1_ABS_Z,
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SRC1_SEL_Z,
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PRED_SEL_Z,
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UPDATE_EXEC_MASK_W,
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UPDATE_PREDICATE_W,
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WRITE_W,
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OMOD_W,
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DST_REL_W,
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CLAMP_W,
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SRC0_W,
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SRC0_NEG_W,
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SRC0_REL_W,
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SRC0_ABS_W,
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SRC0_SEL_W,
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SRC1_W,
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SRC1_NEG_W,
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SRC1_REL_W,
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SRC1_ABS_W,
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SRC1_SEL_W,
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PRED_SEL_W,
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IMM_0,
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IMM_1,
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VEC_COUNT
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};
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}
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//===----------------------------------------------------------------------===//
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// Config register definitions
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//===----------------------------------------------------------------------===//
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#define R_02880C_DB_SHADER_CONTROL 0x02880C
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#define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6)
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// These fields are the same for all shader types and families.
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#define S_NUM_GPRS(x) (((x) & 0xFF) << 0)
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#define S_STACK_SIZE(x) (((x) & 0xFF) << 8)
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//===----------------------------------------------------------------------===//
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// R600, R700 Registers
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//===----------------------------------------------------------------------===//
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#define R_028850_SQ_PGM_RESOURCES_PS 0x028850
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#define R_028868_SQ_PGM_RESOURCES_VS 0x028868
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//===----------------------------------------------------------------------===//
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// Evergreen, Northern Islands Registers
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//===----------------------------------------------------------------------===//
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#define R_028844_SQ_PGM_RESOURCES_PS 0x028844
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#define R_028860_SQ_PGM_RESOURCES_VS 0x028860
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#define R_028878_SQ_PGM_RESOURCES_GS 0x028878
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#define R_0288D4_SQ_PGM_RESOURCES_LS 0x0288d4
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#define R_0288E8_SQ_LDS_ALLOC 0x0288E8
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#endif
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