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llvm-mirror/lib/Target/AMDGPU
Stanislav Mekhanoshin 270ab79b5a [AMDGPU] Fixed isLegalRegOperand() with physregs
This does not change anything at the moment, but needed for
D89170. In that change I am probing a physical SGPR to see if
it is legal. RC is SReg_32, but DRC for scratch instructions
is SReg_32_XEXEC_HI and test fails.

That is sufficient just to check if DRC contains a register
here in case of physreg. Physregs also do not use subregs
so the subreg handling below is irrelevant for these.

Differential Revision: https://reviews.llvm.org/D90064
2020-10-23 11:33:34 -07:00
..
AsmParser AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
Disassembler [AMDGPU] Add MC layer support for v_fmac_legacy_f32 2020-10-13 21:57:33 +01:00
MCTargetDesc [AMDGPU] gfx1032 target 2020-10-15 12:41:18 -07:00
TargetInfo
Utils AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
AMDGPU.h AMDGPU: Remove SIFixupVectorISel pass 2020-08-15 12:11:51 -04:00
AMDGPU.td [AMDGPU] flat scratch ST addressing mode on gfx10 2020-10-19 15:29:52 -07:00
AMDGPUAliasAnalysis.cpp [amdgpu] Enhance AMDGPU AA. 2020-10-20 09:54:12 -04:00
AMDGPUAliasAnalysis.h Remove orphan AMDGPUAAResult::Aliases and AMDGPUAAResult::PathAliases declarations. NFC. 2020-06-25 16:00:44 +01:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAnnotateKernelFeatures.cpp
AMDGPUAnnotateUniformValues.cpp AMDGPU: Put inexpensive ops first in AMDGPUAnnotateUniformValues::visitLoadInst 2020-07-30 14:37:06 -07:00
AMDGPUArgumentUsageInfo.cpp AMDGPU/GlobalISel: Add types to special inputs 2020-07-06 17:00:55 -04:00
AMDGPUArgumentUsageInfo.h AMDGPU: Use MCRegister for preloaded arguments 2020-07-20 13:34:28 -04:00
AMDGPUAsmPrinter.cpp AMDGPU: Lower the threshold reported for maximum stack size exceeded 2020-10-21 12:06:27 -04:00
AMDGPUAsmPrinter.h
AMDGPUAtomicOptimizer.cpp [AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer 2020-09-30 11:09:18 +02:00
AMDGPUCallingConv.td AMDGPU: Implement getNoPreservedMask 2020-10-22 10:17:31 -04:00
AMDGPUCallLowering.cpp AMDGPU/GlobalISel: Stop using G_EXTRACT in argument lowering 2020-08-06 09:55:35 -04:00
AMDGPUCallLowering.h AMDGPU/GlobalISel: Mark GlobalISel classes as final 2020-07-28 11:42:17 -04:00
AMDGPUCodeGenPrepare.cpp SelectionDAG.h - remove unnecessary FunctionLoweringInfo.h include. NFCI. 2020-09-03 18:33:25 +01:00
AMDGPUCombine.td [GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less. 2020-09-09 13:08:16 -07:00
AMDGPUExportClustering.cpp
AMDGPUExportClustering.h
AMDGPUFeatures.td
AMDGPUFixFunctionBitcasts.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUGenRegisterBankInfo.def AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping 2020-08-17 09:53:26 -04:00
AMDGPUGISel.td [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores 2020-08-21 12:26:31 +02:00
AMDGPUGlobalISelUtils.cpp
AMDGPUGlobalISelUtils.h [AMDGPU] Use tablegen for argument indices 2020-10-05 11:50:52 +02:00
AMDGPUHSAMetadataStreamer.cpp AMDGPU: Start interpreting byref on kernel arguments 2020-07-21 18:11:22 -04:00
AMDGPUHSAMetadataStreamer.h AMDGPU: Start interpreting byref on kernel arguments 2020-07-21 18:11:22 -04:00
AMDGPUInline.cpp [NFC] Remove unused GetUnderlyingObject paramenter 2020-07-31 02:10:03 -07:00
AMDGPUInstCombineIntrinsic.cpp [AMDGPU] Add simplification/combines for llvm.amdgcn.fma.legacy 2020-10-23 16:16:13 +01:00
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h [AMDGPU] Use tablegen for argument indices 2020-10-05 11:50:52 +02:00
AMDGPUInstrInfo.td
AMDGPUInstructions.td [AMDGPU] Split R600 and GCN bfe patterns 2020-10-05 09:55:10 +01:00
AMDGPUInstructionSelector.cpp [AMDGPU] Implement hardware bug workaround for image instructions 2020-10-07 07:39:52 -04:00
AMDGPUInstructionSelector.h [AMDGPU] global-isel support for RT 2020-09-24 10:29:45 -07:00
AMDGPUISelDAGToDAG.cpp [AMDGPU] Simplify getNumFlatOffsetBits. NFC. 2020-10-01 15:24:09 +01:00
AMDGPUISelLowering.cpp [AMDGPU] Fix expansion of i16 MULH 2020-10-22 17:05:06 +02:00
AMDGPUISelLowering.h [AMDGPU] Remove unused declaration. NFC. 2020-10-20 16:31:42 +01:00
AMDGPULegalizerInfo.cpp [AMDGPU] Remove fix up operand from SI_ELSE 2020-10-20 19:15:21 +09:00
AMDGPULegalizerInfo.h [AMDGPU] Implement hardware bug workaround for image instructions 2020-10-07 07:39:52 -04:00
AMDGPULibCalls.cpp Use llvm::is_contained where appropriate (NFC) 2020-07-27 10:20:44 -07:00
AMDGPULibFunc.cpp
AMDGPULibFunc.h
AMDGPULowerIntrinsics.cpp AMDGPU: Use caller subtarget, not intrinsic declaration 2020-08-27 16:42:09 -04:00
AMDGPULowerKernelArguments.cpp AMDGPU: Start interpreting byref on kernel arguments 2020-07-21 18:11:22 -04:00
AMDGPULowerKernelAttributes.cpp
AMDGPUMachineCFGStructurizer.cpp [AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy 2020-08-21 10:14:35 +01:00
AMDGPUMachineFunction.cpp [amdgpu] Add codegen support for HIP dynamic shared memory. 2020-08-20 21:29:18 -04:00
AMDGPUMachineFunction.h [amdgpu] Add codegen support for HIP dynamic shared memory. 2020-08-20 21:29:18 -04:00
AMDGPUMachineModuleInfo.cpp
AMDGPUMachineModuleInfo.h
AMDGPUMacroFusion.cpp
AMDGPUMacroFusion.h
AMDGPUMCInstLower.cpp AMDGPU: Increase branch size estimate with offset bug 2020-10-23 10:34:24 -04:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
AMDGPUPerfHintAnalysis.cpp
AMDGPUPerfHintAnalysis.h
AMDGPUPostLegalizerCombiner.cpp AMDGPU/GlobalISel: Fix using post-legal combiner without LegalizerInfo 2020-08-17 09:19:22 -04:00
AMDGPUPreLegalizerCombiner.cpp AMDGPU/GlobalISel: Mark GlobalISel classes as final 2020-07-28 11:42:17 -04:00
AMDGPUPrintfRuntimeBinding.cpp AMDGPUPrintfRuntimeBinding.cpp - drop unnecessary casts/dyn_casts. NFCI. 2020-09-15 14:49:04 +01:00
AMDGPUPromoteAlloca.cpp [NFC] Remove unused GetUnderlyingObject paramenter 2020-07-31 02:10:03 -07:00
AMDGPUPropagateAttributes.cpp AMDGPU: Propagate amdgpu-flat-work-group-size attributes 2020-10-21 12:06:24 -04:00
AMDGPUPTNote.h
AMDGPURegBankCombiner.cpp AMDGPU/GlobalISel: Mark GlobalISel classes as final 2020-07-28 11:42:17 -04:00
AMDGPURegisterBankInfo.cpp [AMDGPU] Add new llvm.amdgcn.fma.legacy intrinsic 2020-10-16 17:10:21 +01:00
AMDGPURegisterBankInfo.h AMDGPU/GlobalISel: Start trying to handle AGPR bank 2020-08-06 12:39:50 -04:00
AMDGPURegisterBanks.td AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank 2020-07-28 16:49:55 -04:00
AMDGPURewriteOutArguments.cpp
AMDGPUSearchableTables.td AMDGPU: Define raw/struct variants of buffer atomic fadd 2020-08-06 13:36:19 -04:00
AMDGPUSubtarget.cpp AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
AMDGPUSubtarget.h AMDGPU: Lower the threshold reported for maximum stack size exceeded 2020-10-21 12:06:27 -04:00
AMDGPUTargetMachine.cpp [HazardRec] Allow inserting multiple wait-states simultaneously 2020-10-20 17:03:47 -07:00
AMDGPUTargetMachine.h Support addrspacecast initializers with isNoopAddrSpaceCast 2020-07-31 10:42:43 -04:00
AMDGPUTargetObjectFile.cpp
AMDGPUTargetObjectFile.h
AMDGPUTargetTransformInfo.cpp [AMDGPU] Add amdgpu specific loop threshold metadata 2020-10-22 17:21:32 +01:00
AMDGPUTargetTransformInfo.h [AMDGPU] Add simplification/combines for llvm.amdgcn.fma.legacy 2020-10-23 16:16:13 +01:00
AMDGPUUnifyDivergentExitNodes.cpp Reland "[NFC] SimplifyCFGOptions: drop multi-parameter ctor, use default member-init" 2020-07-16 13:40:01 +03:00
AMDGPUUnifyMetadata.cpp Use llvm::is_contained where appropriate (NFC) 2020-07-27 10:20:44 -07:00
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
BUFInstructions.td [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. 2020-10-21 09:56:43 +01:00
CaymanInstructions.td [AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM 2020-07-08 19:14:49 +01:00
CMakeLists.txt AMDGPU: Remove SIFixupVectorISel pass 2020-08-15 12:11:51 -04:00
DSInstructions.td [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. 2020-10-21 09:56:43 +01:00
EvergreenInstructions.td [AMDGPU] Split R600 and GCN bfe patterns 2020-10-05 09:55:10 +01:00
FLATInstructions.td [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. 2020-10-21 09:56:43 +01:00
GCNDPPCombine.cpp AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
GCNHazardRecognizer.cpp [AMDGPU] Avoid inserting noops during scheduling 2020-10-20 17:11:36 -07:00
GCNHazardRecognizer.h [AMDGPU] prefer non-mfma in post-RA schedule 2020-07-29 12:17:50 -07:00
GCNILPSched.cpp
GCNIterativeScheduler.cpp
GCNIterativeScheduler.h
GCNMinRegStrategy.cpp Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" 2020-09-21 13:33:05 +02:00
GCNNSAReassign.cpp [NFC][MC] Use MCRegister in LiveRangeMatrix 2020-10-12 08:54:36 -07:00
GCNProcessors.td [AMDGPU] gfx1032 target 2020-10-15 12:41:18 -07:00
GCNRegBankReassign.cpp [NFC][MC] Use MCRegister in LiveRangeMatrix 2020-10-12 08:54:36 -07:00
GCNRegPressure.cpp [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
GCNRegPressure.h [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
GCNSchedStrategy.cpp [AMDGPU] Fix not rescheduling without clustering 2020-08-07 11:15:58 -07:00
GCNSchedStrategy.h
InstCombineTables.td [InstCombine] Move target-specific inst combining 2020-07-22 15:59:49 +02:00
LLVMBuild.txt
MIMGInstructions.td [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. 2020-10-21 09:56:43 +01:00
R600.td
R600AsmPrinter.cpp
R600AsmPrinter.h
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600FrameLowering.cpp
R600FrameLowering.h
R600InstrFormats.td
R600InstrInfo.cpp Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate 2020-10-21 11:52:47 +01:00
R600InstrInfo.h Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate 2020-10-21 11:52:47 +01:00
R600Instructions.td [NFC] Remove unused GetUnderlyingObject paramenter 2020-07-31 02:10:03 -07:00
R600ISelLowering.cpp [AMDGPU] Use cast instead of dyn_cast 2020-09-24 15:20:49 +01:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
R600MachineScheduler.h [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
R600OpenCLImageTypeLoweringPass.cpp
R600OptimizeVectorRegisters.cpp AMDGPU: Use Register 2020-06-30 12:13:08 -04:00
R600Packetizer.cpp
R600Processors.td
R600RegisterInfo.cpp [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
R600RegisterInfo.h [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
R600RegisterInfo.td
R600Schedule.td
R700Instructions.td
SIAddIMGInit.cpp [AMDGPU] gfx1030 RT support 2020-09-16 11:40:58 -07:00
SIAnnotateControlFlow.cpp
SIDefines.h [AMDGPU][MC] Corrected parser to avoid generation of excessive error messages 2020-09-02 19:42:18 +03:00
SIFixSGPRCopies.cpp [AMDGPU] Fix merging m0 inits 2020-09-23 09:13:43 +02:00
SIFixVGPRCopies.cpp
SIFoldOperands.cpp [AMDGPU] More codegen patterns for v2i16/v2f16 build_vector 2020-09-22 10:41:38 +01:00
SIFormMemoryClauses.cpp [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
SIFrameLowering.cpp [AMDGPU] Use isLegalMUBUFImmOffset more 2020-10-08 14:31:44 +02:00
SIFrameLowering.h AMDGPU: Correct prolog SP initialization logic 2020-08-05 15:47:53 -04:00
SIInsertHardClauses.cpp
SIInsertSkips.cpp [AMDGPU] SIInsertSkips: Refactor early exit block creation 2020-10-06 09:44:55 +09:00
SIInsertWaitcnts.cpp [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
SIInstrFormats.td [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. 2020-10-21 09:56:43 +01:00
SIInstrInfo.cpp [AMDGPU] Fixed isLegalRegOperand() with physregs 2020-10-23 11:33:34 -07:00
SIInstrInfo.h [HazardRec] Allow inserting multiple wait-states simultaneously 2020-10-20 17:03:47 -07:00
SIInstrInfo.td [AMDGPU] Refactor SOPC & SOPP .td for extension 2020-10-21 12:35:52 -04:00
SIInstructions.td [AMDGPU] Remove fix up operand from SI_ELSE 2020-10-20 19:15:21 +09:00
SIISelLowering.cpp [AMDGPU] Do not generate S_CMP_LG_U64 on gfx7 2020-10-19 14:44:31 +02:00
SIISelLowering.h [AMDGPU] Implement hardware bug workaround for image instructions 2020-10-07 07:39:52 -04:00
SILoadStoreOptimizer.cpp [AMDGPU] gfx1030 RT support 2020-09-16 11:40:58 -07:00
SILowerControlFlow.cpp [AMDGPU] Remove fix up operand from SI_ELSE 2020-10-20 19:15:21 +09:00
SILowerI1Copies.cpp [AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy 2020-08-21 10:14:35 +01:00
SILowerSGPRSpills.cpp [AMDGPU] Remove getAllVGPR32() which cannot handle Accum VGPRs properly 2020-10-20 23:15:24 +05:30
SIMachineFunctionInfo.cpp AMDGPU: Fix not always reserving VGPRs used for SGPR spilling 2020-10-22 10:19:19 -04:00
SIMachineFunctionInfo.h [amdgpu] Add codegen support for HIP dynamic shared memory. 2020-08-20 21:29:18 -04:00
SIMachineScheduler.cpp [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
SIMachineScheduler.h Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" 2020-09-21 13:33:05 +02:00
SIMemoryLegalizer.cpp [NFC][AMDGPU] Reorder SIMemoryLegalizer functions to be consistent 2020-10-22 05:39:18 +00:00
SIModeRegister.cpp [AMDGPU] Enable scheduling around FP MODE-setting instructions 2020-09-16 16:10:47 +01:00
SIOptimizeExecMasking.cpp AMDGPU: Don't sometimes allow instructions before lowered si_end_cf 2020-09-18 13:43:01 -04:00
SIOptimizeExecMaskingPreRA.cpp [AMDGPU] Remove fix up operand from SI_ELSE 2020-10-20 19:15:21 +09:00
SIPeepholeSDWA.cpp [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister 2020-08-20 17:59:11 +01:00
SIPostRABundler.cpp
SIPreAllocateWWMRegs.cpp [NFC][MC] Use MCRegister in LiveRangeMatrix 2020-10-12 08:54:36 -07:00
SIPreEmitPeephole.cpp [AMDGPU] Fix missed SI_RETURN_TO_EPILOG in pre-emit peephole 2020-08-13 21:52:41 +09:00
SIProgramInfo.h
SIRegisterInfo.cpp AMDGPU: Fix not always reserving VGPRs used for SGPR spilling 2020-10-22 10:19:19 -04:00
SIRegisterInfo.h AMDGPU: Implement getNoPreservedMask 2020-10-22 10:17:31 -04:00
SIRegisterInfo.td [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. 2020-10-21 09:56:43 +01:00
SIRemoveShortExecBranches.cpp
SISchedule.td [AMDGPU] Add XDL resource to scheduling model 2020-09-14 13:48:54 -07:00
SIShrinkInstructions.cpp [AMDGPU] Fixed v_swap_b32 match 2020-10-21 10:14:24 -07:00
SIWholeQuadMode.cpp [AMDGPU] Remove fix up operand from SI_ELSE 2020-10-20 19:15:21 +09:00
SMInstructions.td
SOPInstructions.td AMDGPU: Increase branch size estimate with offset bug 2020-10-23 10:34:24 -04:00
VIInstrFormats.td
VOP1Instructions.td [AMDGPU] Removed s_mov_regrd and mov_fed opcodes 2020-07-17 19:52:54 +03:00
VOP2Instructions.td [AMDGPU] Add MC layer support for v_fmac_legacy_f32 2020-10-13 21:57:33 +01:00
VOP3Instructions.td [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. 2020-10-21 09:56:43 +01:00
VOP3PInstructions.td [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. 2020-10-21 09:56:43 +01:00
VOPCInstructions.td
VOPInstructions.td [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. 2020-10-21 09:56:43 +01:00