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2fa78b38b2
These inserters inserted some instructions to zero some registers and copied from virtual registers to physical registers. This change instead inserts the zeros directly into the DAG at lowering time using new ISD opcodes that take the extra zeroes as inputs. The zeros will then go through isel on their own to select the MOV32r0 pseudo. Then we just need to mention the physical registers directly in the isel patterns and the isel table and InstrEmitter will take care of inserting the necessary copies to/from physical registers. llvm-svn: 357659
37 lines
1.4 KiB
LLVM
37 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=knl --show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,X64
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declare i32 @llvm.x86.rdpkru()
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declare void @llvm.x86.wrpkru(i32)
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define void @test_x86_wrpkru(i32 %src) {
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; X86-LABEL: test_x86_wrpkru:
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; X86: ## %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-NEXT: xorl %edx, %edx ## encoding: [0x31,0xd2]
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; X86-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
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; X86-NEXT: wrpkru ## encoding: [0x0f,0x01,0xef]
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; X86-NEXT: retl ## encoding: [0xc3]
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;
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; X64-LABEL: test_x86_wrpkru:
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; X64: ## %bb.0:
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; X64-NEXT: movl %edi, %eax ## encoding: [0x89,0xf8]
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; X64-NEXT: xorl %edx, %edx ## encoding: [0x31,0xd2]
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; X64-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
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; X64-NEXT: wrpkru ## encoding: [0x0f,0x01,0xef]
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; X64-NEXT: retq ## encoding: [0xc3]
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call void @llvm.x86.wrpkru(i32 %src)
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ret void
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}
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define i32 @test_x86_rdpkru() {
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; CHECK-LABEL: test_x86_rdpkru:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
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; CHECK-NEXT: rdpkru ## encoding: [0x0f,0x01,0xee]
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; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call i32 @llvm.x86.rdpkru()
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ret i32 %res
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}
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