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686c8a92c9
Summary: Kill instructions sometimes do use SCC in unusual circumstances, when v_cmpx cannot be used due to the operands that are involved. Additionally, even if SCC was never defined by the expansion, kill pseudos could previously occur between an s_cmp and an s_cbranch_scc, which breaks the SCC liveness tracking when the pseudo is expanded to split the basic block. While it would be possible to explicitly mark the SCC as live-in for the successor basic block, it's simpler to just mark the pseudo as using SCC, so that such a sequence is never emitted by instruction selection in the first place. A similar issue affects indirect source/dest pseudos in principle, although I haven't been able to come up with a test case where it actually matters (this affects instruction selection, so a MIR test can't be used). Fixes: dEQP-GLES3.functional.shaders.discard.dynamic_loop_always Change-Id: Ica8d82ecff1a763b892a1112cf1b06c948863a4f Reviewers: arsenm, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D47761 llvm-svn: 335223
41 lines
883 B
YAML
41 lines
883 B
YAML
# RUN: llc -march=amdgcn -mcpu=polaris10 -run-pass si-insert-skips -amdgpu-skip-threshold=1 %s -o - | FileCheck %s
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# https://bugs.freedesktop.org/show_bug.cgi?id=99019
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--- |
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define amdgpu_ps void @kill_uncond_branch() {
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ret void
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}
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...
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---
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# CHECK-LABEL: name: kill_uncond_branch
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# CHECK: bb.0:
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# CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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# CHECK: bb.1:
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# CHECK: V_CMPX_LE_F32_e32
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# CHECK-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit $exec
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# CHECK: bb.3:
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# CHECK-NEXT: EXP_DONE
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# CHECK: S_ENDPGM
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# CHECK: bb.2:
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# CHECK: S_ENDPGM
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name: kill_uncond_branch
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body: |
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bb.0:
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successors: %bb.1
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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bb.1:
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successors: %bb.2
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM
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