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https://github.com/RPCS3/llvm-mirror.git
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141144803d
This change attempts to shrink scalar AND, OR and XOR instructions which take an immediate that isn't inlineable. It performs: AND s0, s0, ~(1 << n) -> BITSET0 s0, n OR s0, s0, (1 << n) -> BITSET1 s0, n AND s0, s1, x -> ANDN2 s0, s1, ~x OR s0, s1, x -> ORN2 s0, s1, ~x XOR s0, s1, x -> XNOR s0, s1, ~x In particular, this catches setting and clearing the sign bit for fabs (and x, 0x7ffffffff -> bitset0 x, 31 and or x, 0x80000000 -> bitset1 x, 31). llvm-svn: 348601
214 lines
7.6 KiB
LLVM
214 lines
7.6 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SICIVI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,SICIVI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SICIVI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; GCN-LABEL: {{^}}local_i32_load
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28
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; GCN: buffer_store_dword [[REG]],
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define amdgpu_kernel void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
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%gep = getelementptr i32, i32 addrspace(3)* %in, i32 7
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%val = load i32, i32 addrspace(3)* %gep, align 4
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}local_i32_load_0_offset
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}}
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; GCN: buffer_store_dword [[REG]],
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define amdgpu_kernel void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
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%val = load i32, i32 addrspace(3)* %in, align 4
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}local_i8_load_i16_max_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535
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; GCN: buffer_store_byte [[REG]],
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define amdgpu_kernel void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
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%gep = getelementptr i8, i8 addrspace(3)* %in, i32 65535
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%val = load i8, i8 addrspace(3)* %gep, align 4
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store i8 %val, i8 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}local_i8_load_over_i16_max_offset:
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; SICIVI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
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; SI, which is why it is being OR'd with the base pointer.
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; SI-DAG: s_bitset1_b32 [[ADDR:s[0-9]+]], 16
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; CI-DAG: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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; VI-DAG: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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; GFX9-DAG: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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; GCN-DAG: v_mov_b32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
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; GCN: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]]
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; GCN: buffer_store_byte [[REG]],
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define amdgpu_kernel void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
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%gep = getelementptr i8, i8 addrspace(3)* %in, i32 65536
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%val = load i8, i8 addrspace(3)* %gep, align 4
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store i8 %val, i8 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}local_i64_load:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56
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; GCN: buffer_store_dwordx2 [[REG]],
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define amdgpu_kernel void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
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%gep = getelementptr i64, i64 addrspace(3)* %in, i32 7
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%val = load i64, i64 addrspace(3)* %gep, align 8
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_i64_load_0_offset
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}
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; GCN: buffer_store_dwordx2 [[REG]],
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define amdgpu_kernel void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
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%val = load i64, i64 addrspace(3)* %in, align 8
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_f64_load:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56
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; GCN: buffer_store_dwordx2 [[REG]],
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define amdgpu_kernel void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
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%gep = getelementptr double, double addrspace(3)* %in, i32 7
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%val = load double, double addrspace(3)* %gep, align 8
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_f64_load_0_offset
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}
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; GCN: buffer_store_dwordx2 [[REG]],
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define amdgpu_kernel void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
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%val = load double, double addrspace(3)* %in, align 8
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_i64_store:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56
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define amdgpu_kernel void @local_i64_store(i64 addrspace(3)* %out) nounwind {
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%gep = getelementptr i64, i64 addrspace(3)* %out, i32 7
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store i64 5678, i64 addrspace(3)* %gep, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_i64_store_0_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
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store i64 1234, i64 addrspace(3)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_f64_store:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56
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define amdgpu_kernel void @local_f64_store(double addrspace(3)* %out) nounwind {
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%gep = getelementptr double, double addrspace(3)* %out, i32 7
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store double 16.0, double addrspace(3)* %gep, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_f64_store_0_offset
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
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store double 20.0, double addrspace(3)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_v2i64_store:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:14 offset1:15
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; GCN: s_endpgm
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define amdgpu_kernel void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
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%gep = getelementptr <2 x i64>, <2 x i64> addrspace(3)* %out, i32 7
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store <2 x i64> <i64 5678, i64 5678>, <2 x i64> addrspace(3)* %gep, align 16
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ret void
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}
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; GCN-LABEL: {{^}}local_v2i64_store_0_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:1
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; GCN: s_endpgm
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define amdgpu_kernel void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
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store <2 x i64> <i64 1234, i64 1234>, <2 x i64> addrspace(3)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}local_v4i64_store:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:30 offset1:31
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; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:28 offset1:29
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; GCN: s_endpgm
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define amdgpu_kernel void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
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%gep = getelementptr <4 x i64>, <4 x i64> addrspace(3)* %out, i32 7
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store <4 x i64> <i64 5678, i64 5678, i64 5678, i64 5678>, <4 x i64> addrspace(3)* %gep, align 16
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ret void
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}
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; GCN-LABEL: {{^}}local_v4i64_store_0_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:2 offset1:3
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; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:1
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; GCN: s_endpgm
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define amdgpu_kernel void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind {
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store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, <4 x i64> addrspace(3)* %out, align 16
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ret void
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}
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