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109 lines
4.8 KiB
LLVM
109 lines
4.8 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; XXX - Why the packing?
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; GCN-LABEL: {{^}}scalar_to_vector_v2i32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]],
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; GCN: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 16, [[VAL]]
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; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[SHR]]
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; GCN: v_or_b32_e32 v[[OR:[0-9]+]], [[SHR]], [[SHL]]
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; GCN: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[OR]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[OR]]:[[COPY]]{{\]}}
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define amdgpu_kernel void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%tmp1 = load i32, i32 addrspace(1)* %in, align 4
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%bc = bitcast i32 %tmp1 to <2 x i16>
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%tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}scalar_to_vector_v2f32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]],
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; GCN: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]]
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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%tmp1 = load float, float addrspace(1)* %in, align 4
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%bc = bitcast float %tmp1 to <2 x i16>
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%tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}scalar_to_vector_v4i16:
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; VI: v_lshlrev_b16_e32
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; VI: v_lshlrev_b16_e32
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; VI: v_or_b32_e32
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; VI: v_lshlrev_b32
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; VI: v_or_b32_sdwa
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; VI: v_or_b32_sdwa
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define amdgpu_kernel void @scalar_to_vector_v4i16() {
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bb:
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%tmp = load <2 x i8>, <2 x i8> addrspace(1)* undef, align 1
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%tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
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store <8 x i8> %tmp2, <8 x i8> addrspace(1)* undef, align 8
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ret void
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}
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; GCN-LABEL: {{^}}scalar_to_vector_v4f16:
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; VI: v_lshlrev_b16_e32
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; VI: v_lshlrev_b16_e32
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; VI: v_or_b32_e32
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; VI: v_lshlrev_b32
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; VI: v_or_b32_sdwa
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; VI: v_or_b32_sdwa
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define amdgpu_kernel void @scalar_to_vector_v4f16() {
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bb:
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%load = load half, half addrspace(1)* undef, align 1
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%tmp = bitcast half %load to <2 x i8>
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%tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
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store <8 x i8> %tmp2, <8 x i8> addrspace(1)* undef, align 8
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ret void
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}
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; Getting a SCALAR_TO_VECTOR seems to be tricky. These cases managed
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; to produce one, but for some reason never made it to selection.
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; define amdgpu_kernel void @scalar_to_vector_test2(<8 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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; %tmp1 = load i32, i32 addrspace(1)* %in, align 4
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; %bc = bitcast i32 %tmp1 to <4 x i8>
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; %tmp2 = shufflevector <4 x i8> %bc, <4 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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; store <8 x i8> %tmp2, <8 x i8> addrspace(1)* %out, align 4
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; ret void
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; }
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; define amdgpu_kernel void @scalar_to_vector_test3(<4 x i32> addrspace(1)* %out) nounwind {
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; %newvec0 = insertelement <2 x i64> undef, i64 12345, i32 0
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; %newvec1 = insertelement <2 x i64> %newvec0, i64 undef, i32 1
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; %bc = bitcast <2 x i64> %newvec1 to <4 x i32>
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; %add = add <4 x i32> %bc, <i32 1, i32 2, i32 3, i32 4>
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; store <4 x i32> %add, <4 x i32> addrspace(1)* %out, align 16
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; ret void
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; }
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; define amdgpu_kernel void @scalar_to_vector_test4(<8 x i16> addrspace(1)* %out) nounwind {
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; %newvec0 = insertelement <4 x i32> undef, i32 12345, i32 0
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; %bc = bitcast <4 x i32> %newvec0 to <8 x i16>
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; %add = add <8 x i16> %bc, <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>
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; store <8 x i16> %add, <8 x i16> addrspace(1)* %out, align 16
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; ret void
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; }
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; define amdgpu_kernel void @scalar_to_vector_test5(<4 x i16> addrspace(1)* %out) nounwind {
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; %newvec0 = insertelement <2 x i32> undef, i32 12345, i32 0
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; %bc = bitcast <2 x i32> %newvec0 to <4 x i16>
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; %add = add <4 x i16> %bc, <i16 1, i16 2, i16 3, i16 4>
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; store <4 x i16> %add, <4 x i16> addrspace(1)* %out, align 16
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; ret void
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; }
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define amdgpu_kernel void @scalar_to_vector_test6(<2 x half> addrspace(1)* %out, i8 zeroext %val) nounwind {
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%newvec0 = insertelement <4 x i8> undef, i8 %val, i32 0
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%bc = bitcast <4 x i8> %newvec0 to <2 x half>
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store <2 x half> %bc, <2 x half> addrspace(1)* %out
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ret void
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}
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