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https://github.com/RPCS3/llvm-mirror.git
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aee5f0fc5d
- Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
190 lines
4.4 KiB
LLVM
190 lines
4.4 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
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; RUN: < %s -verify-machineinstrs | FileCheck %s
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define void @testeq(i32, i32) {
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; CHECK-LABEL: testeq:
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: beq $[[REG0]], $[[REG1]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp eq i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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define void @testne(i32, i32) {
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; CHECK-LABEL: testne:
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: bne $[[REG0]], $[[REG1]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp ne i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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define void @testugt(i32, i32) {
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; CHECK-LABEL: testugt:
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
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; CHECK: bnez $[[REG2]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp ugt i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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define void @testuge(i32, i32) {
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; CHECK-LABEL: testuge:
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
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; CHECK: beqz $[[REG2]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp uge i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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define void @testult(i32, i32) {
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; CHECK-LABEL: testult:
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
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; CHECK: bnez $[[REG2]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp ult i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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define void @testule(i32, i32) {
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
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; CHECK: beqz $[[REG2]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp ule i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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define void @testsgt(i32, i32) {
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; CHECK-LABEL: testsgt:
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: negu $[[REG2:[0-9]+]], $[[REG0]]
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: negu $[[REG3:[0-9]+]], $[[REG1]]
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; CHECK: slt $[[REG4:[0-9]+]], $[[REG3]], $[[REG2]]
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; CHECK: bnez $[[REG4]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp sgt i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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define void @testsge(i32, i32) {
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; CHECK-LABEL: testsge:
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: negu $[[REG0]], $[[REG0]]
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: negu $[[REG1]], $[[REG1]]
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; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
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; CHECK: beqz $[[REG2]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp sge i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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define void @testslt(i32, i32) {
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; CHECK-LABEL: testslt:
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: negu $[[REG0]], $[[REG0]]
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: negu $[[REG1]], $[[REG1]]
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; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
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; CHECK: bnez $[[REG2]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp slt i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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define void @testsle(i32, i32) {
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; CHECK-LABEL: testsle:
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; CHECK: andi $[[REG0:[0-9]+]], $4, 1
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; CHECK: negu $[[REG2:[0-9]+]], $[[REG0]]
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; CHECK: andi $[[REG1:[0-9]+]], $5, 1
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; CHECK: negu $[[REG3:[0-9]+]], $[[REG1]]
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; CHECK: slt $[[REG4:[0-9]+]], $[[REG3]], $[[REG2]]
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; CHECK: beqz $[[REG4]],
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%3 = trunc i32 %0 to i1
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%4 = trunc i32 %1 to i1
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%5 = icmp sle i1 %3, %4
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br i1 %5, label %end, label %trap
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trap:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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declare void @llvm.trap()
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