mirror of
https://github.com/RPCS3/llvm-mirror.git
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0c16dcd701
This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO as well as ADDCARRY/SUBCARRY on top of the new CC implementation. In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead of the old ADDC/ADDE logic, which means we no longer need to use "glue" links for those instructions. This also allows making full use of the memory-based instructions like ALSI, which couldn't be recognized due to limitations in the DAG matcher previously. Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to directly using the ADD instructions and checking for a CC 3 result. llvm-svn: 331203
326 lines
10 KiB
LLVM
326 lines
10 KiB
LLVM
; Test 32-bit subtraction in which the second operand is variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i32 @foo()
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; Check SLR.
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define zeroext i1 @f1(i32 %dummy, i32 %a, i32 %b, i32 *%res) {
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; CHECK-LABEL: f1:
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; CHECK: slr %r3, %r4
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check using the overflow result for a branch.
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define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%res) {
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; CHECK-LABEL: f2:
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; CHECK: slr %r3, %r4
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; CHECK: st %r3, 0(%r5)
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; CHECK: jgle foo@PLT
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; CHECK: br %r14
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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br i1 %obit, label %call, label %exit
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call:
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tail call i32 @foo()
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br label %exit
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exit:
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ret void
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}
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; ... and the same with the inverted direction.
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define void @f3(i32 %dummy, i32 %a, i32 %b, i32 *%res) {
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; CHECK-LABEL: f3:
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; CHECK: slr %r3, %r4
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; CHECK: st %r3, 0(%r5)
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; CHECK: jgnle foo@PLT
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; CHECK: br %r14
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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br i1 %obit, label %exit, label %call
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call:
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tail call i32 @foo()
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br label %exit
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exit:
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ret void
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}
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; Check the low end of the SL range.
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define zeroext i1 @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%res) {
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; CHECK-LABEL: f4:
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; CHECK: sl %r3, 0(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%b = load i32, i32 *%src
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the high end of the aligned SL range.
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define zeroext i1 @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%res) {
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; CHECK-LABEL: f5:
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; CHECK: sl %r3, 4092(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 1023
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%b = load i32, i32 *%ptr
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the next word up, which should use SLY instead of SL.
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define zeroext i1 @f6(i32 %dummy, i32 %a, i32 *%src, i32 *%res) {
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; CHECK-LABEL: f6:
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; CHECK: sly %r3, 4096(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 1024
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%b = load i32, i32 *%ptr
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the high end of the aligned SLY range.
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define zeroext i1 @f7(i32 %dummy, i32 %a, i32 *%src, i32 *%res) {
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; CHECK-LABEL: f7:
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; CHECK: sly %r3, 524284(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%b = load i32, i32 *%ptr
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f8(i32 %dummy, i32 %a, i32 *%src, i32 *%res) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r4, 524288
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; CHECK: sl %r3, 0(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%b = load i32, i32 *%ptr
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the high end of the negative aligned SLY range.
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define zeroext i1 @f9(i32 %dummy, i32 %a, i32 *%src, i32 *%res) {
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; CHECK-LABEL: f9:
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; CHECK: sly %r3, -4(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -1
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%b = load i32, i32 *%ptr
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the low end of the SLY range.
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define zeroext i1 @f10(i32 %dummy, i32 %a, i32 *%src, i32 *%res) {
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; CHECK-LABEL: f10:
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; CHECK: sly %r3, -524288(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131072
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%b = load i32, i32 *%ptr
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f11(i32 %dummy, i32 %a, i32 *%src, i32 *%res) {
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; CHECK-LABEL: f11:
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; CHECK: agfi %r4, -524292
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; CHECK: sl %r3, 0(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131073
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%b = load i32, i32 *%ptr
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check that SL allows an index.
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define zeroext i1 @f12(i64 %src, i64 %index, i32 %a, i32 *%res) {
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; CHECK-LABEL: f12:
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; CHECK: sl %r4, 4092({{%r3,%r2|%r2,%r3}})
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; CHECK-DAG: st %r4, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4092
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32, i32 *%ptr
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check that SLY allows an index.
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define zeroext i1 @f13(i64 %src, i64 %index, i32 %a, i32 *%res) {
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; CHECK-LABEL: f13:
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; CHECK: sly %r4, 4096({{%r3,%r2|%r2,%r3}})
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; CHECK-DAG: st %r4, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], -536870912
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32, i32 *%ptr
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check that subtractions of spilled values can use SL rather than SLR.
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define zeroext i1 @f14(i32 *%ptr0) {
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; CHECK-LABEL: f14:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: sl %r2, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i32, i32 *%ptr0, i64 2
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%ptr2 = getelementptr i32, i32 *%ptr0, i64 4
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%ptr3 = getelementptr i32, i32 *%ptr0, i64 6
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%ptr4 = getelementptr i32, i32 *%ptr0, i64 8
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%ptr5 = getelementptr i32, i32 *%ptr0, i64 10
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%ptr6 = getelementptr i32, i32 *%ptr0, i64 12
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%ptr7 = getelementptr i32, i32 *%ptr0, i64 14
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%ptr8 = getelementptr i32, i32 *%ptr0, i64 16
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%ptr9 = getelementptr i32, i32 *%ptr0, i64 18
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%val0 = load i32, i32 *%ptr0
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%val1 = load i32, i32 *%ptr1
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%val2 = load i32, i32 *%ptr2
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%val3 = load i32, i32 *%ptr3
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%val4 = load i32, i32 *%ptr4
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%val5 = load i32, i32 *%ptr5
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%val6 = load i32, i32 *%ptr6
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%val7 = load i32, i32 *%ptr7
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%val8 = load i32, i32 *%ptr8
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%val9 = load i32, i32 *%ptr9
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%ret = call i32 @foo()
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%t0 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %ret, i32 %val0)
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%add0 = extractvalue {i32, i1} %t0, 0
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%obit0 = extractvalue {i32, i1} %t0, 1
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%t1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %add0, i32 %val1)
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%add1 = extractvalue {i32, i1} %t1, 0
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%obit1 = extractvalue {i32, i1} %t1, 1
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%res1 = or i1 %obit0, %obit1
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%t2 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %add1, i32 %val2)
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%add2 = extractvalue {i32, i1} %t2, 0
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%obit2 = extractvalue {i32, i1} %t2, 1
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%res2 = or i1 %res1, %obit2
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%t3 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %add2, i32 %val3)
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%add3 = extractvalue {i32, i1} %t3, 0
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%obit3 = extractvalue {i32, i1} %t3, 1
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%res3 = or i1 %res2, %obit3
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%t4 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %add3, i32 %val4)
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%add4 = extractvalue {i32, i1} %t4, 0
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%obit4 = extractvalue {i32, i1} %t4, 1
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%res4 = or i1 %res3, %obit4
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%t5 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %add4, i32 %val5)
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%add5 = extractvalue {i32, i1} %t5, 0
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%obit5 = extractvalue {i32, i1} %t5, 1
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%res5 = or i1 %res4, %obit5
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%t6 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %add5, i32 %val6)
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%add6 = extractvalue {i32, i1} %t6, 0
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%obit6 = extractvalue {i32, i1} %t6, 1
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%res6 = or i1 %res5, %obit6
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%t7 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %add6, i32 %val7)
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%add7 = extractvalue {i32, i1} %t7, 0
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%obit7 = extractvalue {i32, i1} %t7, 1
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%res7 = or i1 %res6, %obit7
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%t8 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %add7, i32 %val8)
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%add8 = extractvalue {i32, i1} %t8, 0
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%obit8 = extractvalue {i32, i1} %t8, 1
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%res8 = or i1 %res7, %obit8
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%t9 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %add8, i32 %val9)
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%add9 = extractvalue {i32, i1} %t9, 0
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%obit9 = extractvalue {i32, i1} %t9, 1
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%res9 = or i1 %res8, %obit9
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ret i1 %res9
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}
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declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
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