mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 11:33:24 +02:00
7ebfc5f86b
This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
106 lines
2.3 KiB
LLVM
106 lines
2.3 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
|
|
; RUN: -mcpu=a2 | FileCheck %s
|
|
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
|
|
; RUN: -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
|
|
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
|
|
; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9
|
|
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
|
|
target triple = "powerpc64-unknown-linux-gnu"
|
|
|
|
define float @foo(i64 %a) nounwind {
|
|
entry:
|
|
%x = sitofp i64 %a to float
|
|
ret float %x
|
|
|
|
; CHECK: @foo
|
|
; CHECK: std 3,
|
|
; CHECK: lfd [[REG:[0-9]+]],
|
|
; CHECK: fcfids 1, [[REG]]
|
|
; CHECK: blr
|
|
|
|
; CHECK-VSX: @foo
|
|
; CHECK-VSX: std 3,
|
|
; CHECK-VSX: lxsdx [[REG:[0-9]+]],
|
|
; CHECK-VSX: fcfids 1, [[REG]]
|
|
; CHECK-VSX: blr
|
|
|
|
; CHECK-P9: @foo
|
|
; CHECK-P9: std 3,
|
|
; CHECK-P9: lfd [[REG:[0-9]+]],
|
|
; CHECK-P9: xscvsxdsp 1, [[REG]]
|
|
; CHECK-P9: blr
|
|
}
|
|
|
|
define double @goo(i64 %a) nounwind {
|
|
entry:
|
|
%x = sitofp i64 %a to double
|
|
ret double %x
|
|
|
|
; CHECK: @goo
|
|
; CHECK: std 3,
|
|
; CHECK: lfd [[REG:[0-9]+]],
|
|
; CHECK: fcfid 1, [[REG]]
|
|
; CHECK: blr
|
|
|
|
; CHECK-VSX: @goo
|
|
; CHECK-VSX: std 3,
|
|
; CHECK-VSX: lxsdx [[REG:[0-9]+]],
|
|
; CHECK-VSX: xscvsxddp 1, [[REG]]
|
|
; CHECK-VSX: blr
|
|
|
|
; CHECK-P9: @goo
|
|
; CHECK-P9: std 3,
|
|
; CHECK-P9: lfd [[REG:[0-9]+]],
|
|
; CHECK-P9: xscvsxddp 1, [[REG]]
|
|
; CHECK-P9: blr
|
|
}
|
|
|
|
define float @foou(i64 %a) nounwind {
|
|
entry:
|
|
%x = uitofp i64 %a to float
|
|
ret float %x
|
|
|
|
; CHECK: @foou
|
|
; CHECK: std 3,
|
|
; CHECK: lfd [[REG:[0-9]+]],
|
|
; CHECK: fcfidus 1, [[REG]]
|
|
; CHECK: blr
|
|
|
|
; CHECK-VSX: @foou
|
|
; CHECK-VSX: std 3,
|
|
; CHECK-VSX: lxsdx [[REG:[0-9]+]],
|
|
; CHECK-VSX: fcfidus 1, [[REG]]
|
|
; CHECK-VSX: blr
|
|
|
|
; CHECK-P9: @foou
|
|
; CHECK-P9: std 3,
|
|
; CHECK-P9: lfd [[REG:[0-9]+]],
|
|
; CHECK-P9: xscvuxdsp 1, [[REG]]
|
|
; CHECK-P9: blr
|
|
}
|
|
|
|
define double @goou(i64 %a) nounwind {
|
|
entry:
|
|
%x = uitofp i64 %a to double
|
|
ret double %x
|
|
|
|
; CHECK: @goou
|
|
; CHECK: std 3,
|
|
; CHECK: lfd [[REG:[0-9]+]],
|
|
; CHECK: fcfidu 1, [[REG]]
|
|
; CHECK: blr
|
|
|
|
; CHECK-VSX: @goou
|
|
; CHECK-VSX: std 3,
|
|
; CHECK-VSX: lxsdx [[REG:[0-9]+]],
|
|
; CHECK-VSX: xscvuxddp 1, [[REG]]
|
|
; CHECK-VSX: blr
|
|
|
|
; CHECK-P9: @goou
|
|
; CHECK-P9: std 3,
|
|
; CHECK-P9: lfd [[REG:[0-9]+]],
|
|
; CHECK-P9: xscvuxddp 1, [[REG]]
|
|
; CHECK-P9: blr
|
|
}
|
|
|