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cbbfb5ea0e
Attempt to combine CONCAT_VECTORS nodes, which we only really have pre-legalization. This encourages a lot of X86ISD::SUBV_BROADCAST generation, so I've added SimplifyDemandedVectorEltsForTargetNode handling for this at the same time. The X86ISD::VTRUNC regression in shuffle-vs-trunc-256-widen.ll will be handled in a future commit. llvm-svn: 356064
21 lines
797 B
LLVM
21 lines
797 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s
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define <112 x i8> @pr34657(<112 x i8>* %src) local_unnamed_addr {
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; CHECK-LABEL: pr34657:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: vmovups 64(%rsi), %ymm0
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; CHECK-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
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; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm1
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; CHECK-NEXT: vmovups (%rsi), %zmm2
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; CHECK-NEXT: vmovaps %ymm0, 64(%rdi)
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; CHECK-NEXT: vmovaps %zmm2, (%rdi)
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; CHECK-NEXT: vextractf32x4 $2, %zmm1, 96(%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%wide.vec51 = load <112 x i8>, <112 x i8>* %src, align 2
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ret <112 x i8> %wide.vec51
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}
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