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6fae7ed86a
trunc (add X, C ) --> add (trunc X), C' If we're throwing away the top bits of an 'add' instruction, do it in the narrow destination type. This makes the truncate-able opcode list identical to the sibling transform done in IR (in instcombine). This change used to show regressions for x86, but those are gone after D55494. This gets us closer to deleting the x86 custom function (combineTruncatedArithmetic) that does almost the same thing. Differential Revision: https://reviews.llvm.org/D55866 llvm-svn: 350006
45 lines
1.6 KiB
LLVM
45 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
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@ll = local_unnamed_addr global i64 0, align 8
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@x = local_unnamed_addr global i64 2651237805702985558, align 8
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@s1 = local_unnamed_addr global { i8, i8 } { i8 123, i8 5 }, align 2
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@s2 = local_unnamed_addr global { i8, i8 } { i8 -122, i8 3 }, align 2
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define void @PR35765() {
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; CHECK-LABEL: PR35765:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movb {{.*}}(%rip), %cl
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; CHECK-NEXT: addb $-118, %cl
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; CHECK-NEXT: movl $4, %eax
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; CHECK-NEXT: shll %cl, %eax
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; CHECK-NEXT: movzwl {{.*}}(%rip), %ecx
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; CHECK-NEXT: movzwl {{.*}}(%rip), %edx
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; CHECK-NEXT: notl %edx
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; CHECK-NEXT: orl $63488, %edx # imm = 0xF800
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; CHECK-NEXT: movzwl %dx, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: xorl %eax, %edx
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; CHECK-NEXT: movslq %edx, %rax
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: retq
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entry:
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%bf.load.i = load i16, i16* bitcast ({ i8, i8 }* @s1 to i16*), align 2
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%bf.clear.i = and i16 %bf.load.i, 2047
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%conv.i = zext i16 %bf.clear.i to i32
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%sub.i = add nsw i32 %conv.i, -1398
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%shl.i = shl i32 4, %sub.i
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%0 = load i64, i64* @x, align 8
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%bf.load1.i = load i16, i16* bitcast ({ i8, i8 }* @s2 to i16*), align 2
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%bf.clear2.i = and i16 %bf.load1.i, 2047
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%1 = xor i16 %bf.clear2.i, -1
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%neg.i = zext i16 %1 to i64
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%or.i = or i64 %0, %neg.i
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%conv5.i = trunc i64 %or.i to i32
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%conv6.i = and i32 %conv5.i, 65535
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%xor.i = xor i32 %conv6.i, %shl.i
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%conv7.i = sext i32 %xor.i to i64
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store i64 %conv7.i, i64* @ll, align 8
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ret void
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}
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