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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
48 lines
1.3 KiB
LLVM
48 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefixes=X86
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64
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define i64 @test1(i64 %x) nounwind {
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; X86-LABEL: test1:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %edx
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; X86-NEXT: shldl $9, %eax, %edx
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; X86-NEXT: shldl $9, %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test1:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: rolq $9, %rax
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; X64-NEXT: retq
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entry:
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%tmp2 = lshr i64 %x, 55 ; <i64> [#uses=1]
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%tmp4 = shl i64 %x, 9 ; <i64> [#uses=1]
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%tmp5 = or i64 %tmp2, %tmp4 ; <i64> [#uses=1]
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ret i64 %tmp5
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}
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define i64 @test2(i32 %x) nounwind {
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; X86-LABEL: test2:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: roll $10, %eax
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: roll $10, %eax
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; X64-NEXT: retq
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entry:
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%tmp2 = lshr i32 %x, 22 ; <i32> [#uses=1]
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%tmp4 = shl i32 %x, 10 ; <i32> [#uses=1]
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%tmp5 = or i32 %tmp2, %tmp4 ; <i32> [#uses=1]
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%tmp56 = zext i32 %tmp5 to i64 ; <i64> [#uses=1]
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ret i64 %tmp56
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}
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