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a3a32619fb
Now we switch to the subregister in expandPostRAPseudos where we already switched the opcode. This simplifies a few isel patterns that used the pseudo directly. And magically seems to have improved our ability to CSE it in the undef-label.ll test. llvm-svn: 339496
117 lines
3.4 KiB
LLVM
117 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=X64
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; RUN: llc -mtriple=i686-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=I32
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; From source: clang -02
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;__m64 test47(int a)
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;{
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; __m64 x = (a)? (__m64)(7): (__m64)(0);
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; return __builtin_ia32_psllw(x, x);
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;}
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define i64 @test47(i64 %arg) {
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;
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; X64-LABEL: test47:
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; X64: # %bb.0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: testq %rdi, %rdi
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; X64-NEXT: movl $7, %ecx
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; X64-NEXT: cmovneq %rax, %rcx
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; X64-NEXT: movq %rcx, %mm0
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; X64-NEXT: psllw %mm0, %mm0
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; X64-NEXT: movq %mm0, %rax
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; X64-NEXT: retq
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;
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; I32-LABEL: test47:
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; I32: # %bb.0:
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; I32-NEXT: pushl %ebp
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; I32-NEXT: .cfi_def_cfa_offset 8
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; I32-NEXT: .cfi_offset %ebp, -8
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; I32-NEXT: movl %esp, %ebp
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; I32-NEXT: .cfi_def_cfa_register %ebp
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; I32-NEXT: andl $-8, %esp
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; I32-NEXT: subl $16, %esp
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; I32-NEXT: movl 8(%ebp), %eax
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; I32-NEXT: orl 12(%ebp), %eax
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; I32-NEXT: movl $7, %eax
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; I32-NEXT: je .LBB0_2
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; I32-NEXT: # %bb.1:
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; I32-NEXT: xorl %eax, %eax
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; I32-NEXT: .LBB0_2:
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; I32-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; I32-NEXT: movl $0, {{[0-9]+}}(%esp)
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; I32-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; I32-NEXT: psllw %mm0, %mm0
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; I32-NEXT: movq %mm0, (%esp)
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; I32-NEXT: movl (%esp), %eax
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; I32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; I32-NEXT: movl %ebp, %esp
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; I32-NEXT: popl %ebp
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; I32-NEXT: .cfi_def_cfa %esp, 4
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; I32-NEXT: retl
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%cond = icmp eq i64 %arg, 0
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%slct = select i1 %cond, x86_mmx bitcast (i64 7 to x86_mmx), x86_mmx bitcast (i64 0 to x86_mmx)
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%psll = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %slct, x86_mmx %slct)
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%retc = bitcast x86_mmx %psll to i64
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ret i64 %retc
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}
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; From source: clang -O2
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;__m64 test49(int a, long long n, long long m)
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;{
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; __m64 x = (a)? (__m64)(n): (__m64)(m);
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; return __builtin_ia32_psllw(x, x);
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;}
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define i64 @test49(i64 %arg, i64 %x, i64 %y) {
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;
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; X64-LABEL: test49:
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; X64: # %bb.0:
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; X64-NEXT: testq %rdi, %rdi
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; X64-NEXT: cmovneq %rdx, %rsi
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; X64-NEXT: movq %rsi, %mm0
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; X64-NEXT: psllw %mm0, %mm0
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; X64-NEXT: movq %mm0, %rax
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; X64-NEXT: retq
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;
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; I32-LABEL: test49:
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; I32: # %bb.0:
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; I32-NEXT: pushl %ebp
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; I32-NEXT: .cfi_def_cfa_offset 8
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; I32-NEXT: .cfi_offset %ebp, -8
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; I32-NEXT: movl %esp, %ebp
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; I32-NEXT: .cfi_def_cfa_register %ebp
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; I32-NEXT: andl $-8, %esp
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; I32-NEXT: subl $8, %esp
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; I32-NEXT: movl 8(%ebp), %eax
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; I32-NEXT: orl 12(%ebp), %eax
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; I32-NEXT: je .LBB1_1
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; I32-NEXT: # %bb.2:
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; I32-NEXT: leal 24(%ebp), %eax
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; I32-NEXT: jmp .LBB1_3
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; I32-NEXT: .LBB1_1:
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; I32-NEXT: leal 16(%ebp), %eax
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; I32-NEXT: .LBB1_3:
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; I32-NEXT: movq (%eax), %mm0
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; I32-NEXT: psllw %mm0, %mm0
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; I32-NEXT: movq %mm0, (%esp)
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; I32-NEXT: movl (%esp), %eax
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; I32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; I32-NEXT: movl %ebp, %esp
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; I32-NEXT: popl %ebp
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; I32-NEXT: .cfi_def_cfa %esp, 4
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; I32-NEXT: retl
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%cond = icmp eq i64 %arg, 0
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%xmmx = bitcast i64 %x to x86_mmx
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%ymmx = bitcast i64 %y to x86_mmx
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%slct = select i1 %cond, x86_mmx %xmmx, x86_mmx %ymmx
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%psll = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %slct, x86_mmx %slct)
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%retc = bitcast x86_mmx %psll to i64
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ret i64 %retc
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}
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declare x86_mmx @llvm.x86.mmx.psll.w(x86_mmx, x86_mmx)
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