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https://github.com/RPCS3/llvm-mirror.git
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92233f14e9
Summary: In r333455 we added a peephole to fix the corner cases that result from separating base + offset lowering of global address.The peephole didn't handle some of the cases because it only has a basic block view instead of a function level view. This patch replaces that logic with a machine function pass. In addition to handling the original cases it handles uses of the global address across blocks in function and folding an offset from LW\SW instruction. This pass won't run for OptNone compilation, so there will be a negative impact overall vs the old approach at O0. Reviewers: asb, apazos, mgrang Reviewed By: asb Subscribers: MartinMosbeck, brucehoult, the_o, rogfer01, mgorny, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits, edward-jones Differential Revision: https://reviews.llvm.org/D47857 llvm-svn: 335786
35 lines
1.1 KiB
CMake
35 lines
1.1 KiB
CMake
set(LLVM_TARGET_DEFINITIONS RISCV.td)
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tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
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tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
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add_public_tablegen_target(RISCVCommonTableGen)
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add_llvm_target(RISCVCodeGen
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RISCVAsmPrinter.cpp
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RISCVFrameLowering.cpp
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RISCVInstrInfo.cpp
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RISCVISelDAGToDAG.cpp
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RISCVISelLowering.cpp
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RISCVMCInstLower.cpp
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RISCVMergeBaseOffset.cpp
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RISCVRegisterInfo.cpp
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RISCVSubtarget.cpp
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RISCVTargetMachine.cpp
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RISCVTargetObjectFile.cpp
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)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(InstPrinter)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(TargetInfo)
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